IP Library › Granted Patent US 8,492,874
Granted Patent B2
US 8,492,874 · App. 13/021,151 · Granted Jul 23, 2013

High density metal-insulator-metal trench capacitor

Inventors: Je-Hsiung Lan (San Diego, CA); Matthew Michael Nowak (San Diego, CA); Evgeni P. Gousev (San Jose, AZ); Jonghae Kim (San Diego, CA); Clarence Chui (San Jose, CA)
Assignee: QUALCOMM Incorporated
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Quick Facts
Patent No.
US 8,492,874
App. No.
13/021,151
Granted
Jul 23, 2013
Kind
B2
Abstract

Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

Claims (60)

1. An apparatus, comprising:

a substrate;

a first bilayer deposited on the substrate, the first bilayer including a first bilayer layer made of a hard mask material and a second bilayer layer made of an isotropically etchable material;

a trench in the first bilayer, the trench including a vertical portion extending through the first bilayer layer and a concave portion extending through the second bilayer layer and under a portion of the first bilayer layer; and

a capacitor conforming to the vertical portion and the concave portion, the capacitor including:

a first metal-insulator-metal (MIM) conducting layer deposited on the vertical portion and the concave portion,

a first MIM insulating layer deposited on the first conducting layer, and

a second MIM conducting layer deposited on the first insulating layer.

2. The apparatus of claim 1 , further comprising:

a second MIM insulating layer on the second conducting layer; and

a third MIM conducting layer on the second insulating layer.

3. The apparatus of claim 1 , further comprising:

a second bilayer deposited on the first bilayer, in which the trench extends into the second bilayer.

4. The apparatus of claim 1 , in which the first bilayer layer is a silicon dioxide layer and the second bilayer layer is an amorphous silicon layer.

5. The apparatus of claim 1 , in which the capacitor is integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, a fixed location data unit, and/or a Mirasol display.

6. The apparatus of claim 1 , in which said substrate comprises a glass substrate.

7. The apparatus of claim 1 , further comprising:

a semiconductor die including a first portion of a conductive path coupled to the capacitor, and

a printed circuit board including a second portion of the conductive path coupled to the capacitor.

8. The apparatus of claim 7 , in which the capacitor is configured as a bypass capacitor on the conductive path.

9. A method, comprising:

depositing a first bilayer on a substrate, the first bilayer including a first bilayer layer made of hard mask material and a second bilayer layer made of an isotropically etchable material;

etching a trench in the first bilayer, the trench including a concave trench wall portion extending through the second bilayer layer and under a portion of the first bilayer layer;

depositing a first metal-insulator-metal (MIM) conducting layer of a capacitor on concave trench wall portion;

depositing a first MIM capacitor insulating layer of the capacitor on the first conducting layer; and

depositing a second MIM conducting layer of the capacitor on the first insulating layer.

10. The method of claim 9 , in which depositing the first bilayer comprises depositing an amorphous silicon layer and an insulating layer.

11. The method of claim 10 , in which etching the trench comprises isotropically etching the amorphous silicon layer to form the concave trench portion.

12. The method of claim 9 , further comprising:

depositing a second MIM insulating layer on the second conducting layer; and

depositing a third MIM conducting layer on the second insulating layer.

13. The method of claim 9 , further comprising integrating the capacitor into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, a fixed location data unit, and/or a Mirasol display.

14. The method of claim 9 , in which said substrate comprises a glass substrate.

15. The method of claim 9 , further comprising:

coupling a semiconductor die including a first portion of a conductive path to the capacitor, and

coupling a printed circuit board including a second portion of the conductive path to the capacitor.

16. The method of claim 15 , further comprising:

configuring the capacitor as a bypass capacitor on the conductive path.

17. A method, comprising the steps of:

depositing a plurality of bilayers on a substrate, each of the plurality of bilayers including an hard mask layer deposited over an amorphous silicon layer;

patterning a trench in the plurality of bilayers by isotropically etching each of the amorphous silicon layers to form a concave trench wall portion extending between each of the hard mask layers;

depositing a first conducting layer of a metal-insulator-metal (MIM) capacitor on the concave trench wall portion;

depositing a first capacitor insulating layer of the MIM capacitor on the first conducting layer; and

depositing a second conducting layer of the MIM capacitor on the first insulating layer.

18. The method of claim 17 , further comprising the step of integrating the capacitor into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication, systems (PCS) unit, a portable data unit, a fixed location data unit, and/or a Mirasol display.

19. An apparatus, comprising:

a substrate;

a first bilayer coupled to the substrate, the first bilayer including a first bilayer layer made of a hard mask material and a second bilayer layer made of an isotropically etchable material;

a trench in the first bilayer, the trench including a vertical portion extending through the first bilayer layer and a concave portion extending through the second bilayer layer and under a portion of the first bilayer layer; and

means for providing capacitance in the trench, conforming to the vertical portion and the concave portion.

20. The apparatus of claim 19 , in which the first bilayer comprises at least one bilayer of an amorphous silicon layer and an insulating layer.

21. The apparatus of claim 19 in which the substrate comprises a glass substrate.

22. The apparatus of claim 19 , integrated into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, a fixed location data unit, and a Mirasol display.

23. The apparatus of claim 1 , in which the first bilayer layer comprises an anisotropically etchable material, and the second bilayer layer comprises an isotropically etchable material.

24. The apparatus of claim 1 , in which the first bilayer is one of a plurality of stacked bilayers of the same materials:

each of the stacked bilayers includes a first bilayer layer and a second bilayer layer; and

the trench extends through the plurality of stacked bilayers, and the trench includes a concave trench wall portion extending through the second bilayer layer and under the first bilayer layer in each of the stacked bilayers.

25. The method of claim 9 , further comprising:

depositing a plurality of bilayers on the substrate; and

etching the trench in the plurality of bilayers, the trench including a concave trench wall portion extending through a second bilayer layer of each of the plurality of bilayers and under a portion of first bilayer layer of each of the plurality of bilayers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2013
From: LAN, JE-HSIUNG; NOWAK, MATTHEW MICHAEL; GOUSEV, EVGENI PETROVICH; KIM, JONGHAE; CHUI, CLARENCE
To: QUALCOMM INCORPORATED
Reel/Frame 030527/0146 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2011
From: LAN, JE-HSIUNG; NOWAK, MATTHEW MICHAEL; GOUSEV, EVGENI P.; KIN, JONGHAE; CHUI, CLARENCE
To: QUALCOMM INCORPORATED
Reel/Frame 025746/0420 →
Continuity (1)
Related Publication 20120199949A1 · Aug 9, 2012