Method of manufacturing semiconductor package
Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes.
1. A method of manufacturing a semiconductor device, comprising:
mounting a semiconductor chip on a package substrate;
forming a molding member on the semiconductor chip;
forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view;
forming sub-holes between the via holes, the sub-holes being not to expose the top surface of the semiconductor chip; and
forming thermally conductive via plugs in the via holes.
2. The method of claim 1 , wherein the forming the via holes comprises removing portions of the molding member by laser drilling process.
3. The method of claim 1 , wherein the forming the thermally conductive via plugs comprises filling the via holes with a solder material using a reflow process.
4. The method of claim 1 , further comprising:
forming thermally conductive sub-plugs in the sub-holes.
5. The method of claim 4 , wherein the thermally conductive sub-plugs bridge at least two of the thermally conductive via plugs.
6. The method of claim 4 , wherein at least two of the thermally conductive sub-plugs are formed between the thermally conductive via plugs.
7. The method of claim 1 , further comprising:
forming thermal pads on the semiconductor chip to be in contact with the thermally conductive via plugs.
8. The method of claim 7 , further comprising:
forming a chip pad on the semiconductor chip not to be in contact with the thermally conductive via plugs.
9. The method of claim 8 , further comprising:
forming an upper conductive pad on the package substrate, the upper conductive pad being electrically connected with the chip pad via a connection member.
10. The method of claim 7 , wherein at least two of the thermally conductive via plugs are in contact with one of the thermal pads.
11. The method of claim 10 , wherein the chip pad is formed at same level as the thermal pad.
12. The method of claim 1 , wherein the via holes has a tapered shape such that an inner diameter of the holes decreases toward the thermal pads.
13. The method of claim 1 , wherein a top surface of the thermally conductive via plugs is lower than a top surface of the molding member.
14. A method of manufacturing a semiconductor package, comprising:
mounting a semiconductor chip having a plurality of thermal pads on a package substrate;
forming a molding member to cover the semiconductor chip on the package substrate;
forming a plurality of holes in the molding member, at least one of the plurality of holes exposing the thermal pads;
mounting thermally conductive materials on the plurality of holes; and
reflowing the thermally conductive materials to fill the plurality of holes with thermally conductive via plugs.
15. The method of claim 14 , wherein the forming the thermal pads on the semiconductor chip comprises:
forming chip pads on the semiconductor chip;
forming a passivation layer and a first buffer layer on the semiconductor circuit to expose the chip pads;
forming the thermal pads on the first buffer layer; and
forming a second buffer layer on the first buffer layer to expose the thermal pads.
16. A method of manufacturing a semiconductor package, comprising:
preparing a package substrate having an upper conductive pad thereon;
mounting a semiconductor chip having a thermal pad and a chip pad;
electrically connecting the upper conductive pad with the chip pad via a connection member;
encapsulating the semiconductor chip and the connection member using a molding member;
forming a via plug penetrating the molding member to be directly in contact with the thermal pad;
forming a sub-plug in the molding member not to be in contact with the thermal pad,
wherein the via plug and the sub-plug are materially in continuity with each other.
17. The method of claim 16 , wherein the forming the via plug comprises:
forming a via hole penetrating the molding member to expose the thermal pad and a sub-hole penetrating the molding member not to expose the thermal pad and the chip pad; and
forming the via plug in the via hole and the sub-plug in the sub-hole by filling the via hole and the sub-hole with solder materials.
18. The method of claim 17 , wherein the via hole has a greater depth than the sub-hole.