Clock and data recovery system
This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.
1. A clock and data recovery system, comprising:
a plurality of gm cells respectively having an input end and an output end;
a control device, controlling a part of the plurality of gm cells to form a first gm cell, and the control device controlling another part of the plurality of gm cells to form a second gm cell;
a resistor, connecting between the first gm cell and the second gm cell; and
a capacitor, connecting to the second gm cell; wherein the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.
2. The system according to claim 1 , wherein the number of gm cells comprises 7.
3. The system according to claim 2 , wherein the ratio of the first gm cell to the second gm cell is 4 to 3.
4. The system according to claim 1 , wherein the input end is connected to a phase detector.
5. The system according to claim 4 , wherein the clock and data recovery system further comprises a first signal and a second signal, and the first signal and the second signal being connected to the control device and the phase detector.
6. The system according to claim 5 , wherein the phase detector comprises a positive signal, a negative signal, a detector input voltage and a third signal.
7. The system according to claim 6 , wherein the clock and data recovery system further comprises a power source, and the third signal is inputted to the power source.
8. The system according to claim 5 , wherein the second signal comprises a chopper signal.
9. The system according to claim 1 , wherein the polarity of output end connected by the first gm cell comprises positive.
10. The system according to claim 1 , wherein the polarity of output end connected by the second gm cell comprises negative.