Semiconductor device including metal silicide layer and fabrication method thereof

1. A semiconductor device comprising:

a substrate;

a gate structure formed on the substrate;

a channel region below the gate structure in the substrate;

a first source/drain region and a second source/drain region located at opposite side of the gate structure;

a first lightly-doped drain (LDD) junction region formed between the first source/drain region and one end of the channel region;

a second lightly-doped drain (LDD) junction region formed between the second source/drain region and the other end of the channel region;

a metal silicide layer having a first metal formed on the first and second source/drain regions;

an insulating layer formed on the metal silicide layer and the gate structure having a first opening to expose the metal silicide layer; and

a conductive layer having the first metal and filling the first opening to contact the metal silicide layer, wherein the conductive layer includes a barrier layer having the first metal and a contact plug, and wherein the barrier layer is formed on an inner sidewall of the first opening and the contact plug is formed on the barrier layer, and wherein the barrier layer and the contact plug are in direct contact with the metal silicide layer.

2. The semiconductor device of claim 1 , wherein the conductive layer includes the barrier layer formed on an inner sidewall of the first opening and the contact plug formed on the barrier layer and the metal silicide, wherein the barrier layer includes the first metal.

3. The semiconductor device of claim 1 , wherein the conductive layer is a single layer having the first metal.

4. The semiconductor device of claim 1 , wherein the metal silicide layer is further formed on the first and second LDD junction regions.

5. The semiconductor device of claim 1 , wherein the first and second source/drain regions are formed in a recessed region of the substrate, wherein a top surface of the recessed region is positioned at the first LDD junction region and the second LDD junction.

6. The semiconductor device of claim 5 , wherein the metal silicide layer is further formed on the first and second LDD junction region.

7. The semiconductor device of claim 1 , wherein the first metal is a metal selected from the group consisting of titanium (Ti), cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), and tungsten (W).

8. The semiconductor device of claim 1 , wherein the metal silicide layer is self-aligned with an upper surface of the first and second source/drain regions.

9. The semiconductor device of claim 1 , wherein the gate structure has sidewalls on either side of the gate structure and the LDD junction region is formed under the sidewalls of the gate structure.

10. The semiconductor device of claim 9 , wherein the first and second source/drain regions are formed in a recessed region of the substrate, wherein a top surface of the recessed region is aligned with the first and second lightly-doped drain (LDD) junction regions.

11. The semiconductor device of claim 1 , wherein the metal silicide layer has a smaller electrical resistance than that of the first and second source/drain regions, and the metal silicide layer has a thickness less than a junction depth of the first and second source/drain regions.

12. The semiconductor device of claim 1 , wherein the gate structure includes a polysilicon gate layer doped with impurities and a metal silicide gate layer stacked on the polysilicon gate layer.

13. A semiconductor device comprising:

a substrate having an active region and an isolation region;

a plurality of gate stack structures, each of gate stack structures locating between a first source/drain region and a second source/drain region;

a plurality of channel regions under the corresponding gate stack structures, each of channel regions having a first LDD junction region formed between the first source/drain region and one end of the channel region and a second LDD junction region formed between the second source/drain region and the other end of the channel region;

a metal silicide layer having a first metal formed on the active region other than the plurality of gate structures;

an insulating layer having a plurality of openings to expose the metal silicide layer; and

a plurality of conductive layers filling the openings and contacting the metal silicide layer, wherein each of the plurality of conductive layers includes a barrier layer having the first metal and a contact plug, and wherein the barrier layer is formed on an inner sidewall of the plurality of openings and the contact plug is formed on the barrier layer, and wherein the barrier layer and the contact plug are in direct contact with the metal silicide layer.

14. The semiconductor device of claim 13 , wherein the insulating layer includes a second opening which extends along an upper surface of the first and second source/drains and a first opening which is connected to the second opening and vertically extends from the first and second source/drains.

15. The semiconductor device of claim 13 , wherein the insulating layer includes a second opening which extends along an upper surface of the first and second source/drains and a first opening which is connected to the second opening and vertically extends from the first and second source/drains.

16. The semiconductor device of claim 13 , wherein the metal silicide layer is further formed on the first and second LDD junction regions.

17. The semiconductor device of claim 13 , wherein the first and second source/drain regions are formed in a recessed region of the substrate, wherein a top surface of the recessed region is positioned at the first LDD junction region and the second LDD junction.

18. The semiconductor device of claim 17 , wherein the metal silicide layer is further formed on the first and second LDD junction region.

19. The semiconductor device of claim 13 , wherein the metal silicide layer is self-aligned with an upper surface of the first and second source/drain regions.