IP Library › Granted Patent US 8,569,158
Granted Patent B2
US 8,569,158 · App. 13/077,721 · Granted Oct 29, 2013

Method for forming ultra-shallow doping regions by solid phase diffusion

Inventor: Robert D. Clark (Livermore, CA)
Assignee: Tokyo Electron Limited
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Quick Facts
Patent No.
US 8,569,158
App. No.
13/077,721
Granted
Oct 29, 2013
Kind
B2
Abstract

A method for forming an ultra-shallow dopant region in a substrate is provided. In one embodiment, the method includes depositing a dopant layer in direct contact with the substrate, the dopant layer containing an oxide, a nitride, or an oxynitride, where the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi). The method further includes patterning the dopant layer; and forming the ultra-shallow dopant region in the substrate by diffusing the dopant from the patterned dopant layer into the substrate by a thermal treatment.

Claims (12)

1. A method for forming an ultra-shallow dopant region in a substrate, the method comprising:

depositing a dopant layer in direct contact with a recessed feature of the substrate, the dopant layer containing (i) a nitride, or (ii) an oxynitride, wherein the dopant layer contains a dopant selected from aluminum (Al), gallium (Ga), indium (In), thallium (Tl), nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), and bismuth (Bi), wherein in (i) the nitride is deposited by atomic layer deposition (ALD) using a reactant gas containing NH 3 , and wherein in (ii) the oxynitride is deposited by ALD using a reactant gas containing a) H 2 O, O 2 , or O 3 , and NH 3 , or b) NO, NO 2 or N 2 O, and optionally one or more of H 2 O, O 2 , O 3 , and NH 3 ;

patterning the dopant layer; and

forming the ultra-shallow dopant region in the recessed feature of the substrate by diffusing the dopant from the patterned dopant layer into the recessed feature of the substrate by a thermal treatment.

2. The method of claim 1 , further comprising:

removing the patterned dopant layer from the substrate.

3. The method of claim 1 , further comprising

depositing a cap layer on the dopant layer or on the patterned dopant layer.

4. The method of claim 3 , further comprising:

removing the patterned dopant layer and the cap layer from the substrate.

5. The method of claim 1 , wherein the substrate comprises Si, Ge, In, Ga, As, Sb, GaAs, InGaAs, InGaSb, or Si x Ge 1-x wherein 0<x<1.

6. The method of claim 1 , wherein a thickness of the dopant layer is 4 nm or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2011
From: CLARK, ROBERT D
To: TOKYO ELECTRON LIMITED
Reel/Frame 026121/0198 →
Continuity (1)
Related Publication 20120252196A1 · Oct 4, 2012