Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.
1. A method for operating a memory device, comprising: powering-up the memory device in an asynchronous operating mode;
detecting for a clock signal on a write enable signal line of the powered-up memory device;
switching the powered-up memory device to a synchronous operating mode at least partially in response to detecting a clock signal on the write enable signal line; and
transferring data to the memory device in a synchronous manner utilizing a signal on only one more contact of the memory device than the quantity of contacts of the memory device utilized in the asynchronous operating mode.
2. The method of claim 1 , including detecting for the clock signal at least partially in response to a chip enable signal.
3. The method of claim 1 , further comprising transferring data to the memory device in a synchronous manner at least partially in response to the clock signal.
4. The method of claim 1 , including synchronizing data transfer to state transitions of a bidirectional data strobe signal in the synchronous mode.
5. A method for operating a memory device, comprising:
powering-up the memory device in an asynchronous operating mode;
detecting for a clock signal on a write enable signal line of the powered-up memory device;
switching the powered-up memory device to a synchronous operating mode if a clock signal is detected on the write enable signal line;
and transferring data to the memory device in a synchronous manner utilizing a signal on only one more memory device contact than the quantity of contacts utilized in the asynchronous operating mode.
6. The method of claim 5 , wherein a bidirectional data strobe signal is the signal on the only one more memory interface contact.
7. The method of claim 6 , wherein a state of a signal line used to enable reading in the asynchronous operating mode controls direction of data and the bidirectional data strobe signal.
8. A method of operating a memory interface, comprising: powering-up the memory interface in an asynchronous operating mode;
providing a write enable signal on a write enable signal line of the powered-up memory interface;
switching the powered-up memory interface to a synchronous operating mode at least partially in response to detecting a clock signal on the write enable signal line; and
transferring data to the memory interface in a synchronous manner utilizing a signal on only one more contact of the more memory interface than the quantity of contacts of the memory interface utilized in the asynchronous operating mode.
9. A method of operating a memory interface, comprising:
powering-up the memory interface in an asynchronous operating mode;
providing a write enable signal on a write enable signal line of the powered-up memory interface in the asynchronous operating mode;
operating the memory interface in the asynchronous mode until a clock signal is detected on the write enable signal line;
switching the memory interface to a synchronous operating mode if the clock signal is detected on the write enable signal line;
controlling data transfer responsive to the bidirectional data strobe signal line in the synchronous mode; and
disabling the bidirectional data strobe signal line in the asynchronous mode.
10. The method of claim 8 , including detecting for the clock signal on the write enable signal line at least partially in response to a chip enable signal on a chip enable signal line.
11. A method of operating a memory interface, comprising:
powering-up the memory interface in an asynchronous operating mode;
providing a write enable signal on a write enable signal line of the powered-up memory interface in the asynchronous operating mode;
operating the memory interface in the asynchronous mode until a clock signal is detected on the write enable signal line;
operating the memory interface in the synchronous mode while the clock signal is present on the write enable signal line;
providing a read enable signal on a read enable signal line in the asynchronous operating mode; and
providing a write/read signal on the read enable signal line in the synchronous operating mode.
12. The method of claim 8 , including switching the memory interface to a synchronous operating mode responsive to a GET feature command.
13. A memory interface, comprising:
a bi-directional multiplexed bus for communicating command, address, and data information; and
control circuitry to control the command, address, and data information on portions of the bus, and provide a second signal on a second signal line, responsive to at least a first signal on a first signal line,
wherein the memory interface is powered-up in an asynchronous operating mode, and
wherein the control circuitry utilizes the first signal as a write enable signal in an asynchronous mode and as a clock signal in a synchronous mode,
and wherein the control circuitry switches to a synchronous operating mode at least partially in response to detecting the clock signal on the first signal line; and
wherein transferring data to the memory interface in a synchronous manner requires only one more contact on the more memory interface than the quantity of contacts on the memory interface required in the asynchronous operating mode.
14. The memory interface of claim 13 , wherein the control circuitry processes the second signal as a read enable signal in the asynchronous mode and as a write/read signal in the synchronous mode.
15. The memory interface of claim 13 , wherein the control circuitry detects for the clock signal at least partially in response to a chip enable signal.
16. The memory interface of claim 13 , wherein the control circuitry synchronizes data transfer to state transitions of a bidirectional data strobe signal in the synchronous mode.
17. A memory interface, comprising:
a bi-directional multiplexed bus for communicating command, address, and data information; and
control circuitry to control the command, address, and data information on portions of the bus, and provide a second signal on a second signal line, responsive to at least a first signal on a first signal line,
wherein the memory interface is powered-up in an asynchronous operating mode, and
wherein the control circuitry utilizes the first signal as a write enable signal in an asynchronous mode and as a clock signal in a synchronous mode, and
wherein the control circuitry switches to a synchronous operating mode if the clock signal is detected on the first signal line, and
wherein the control circuitry transfers data to the memory device in a synchronous manner utilizing a signal on only one more memory interface contact than a quantity of contacts utilized in the asynchronous operating mode.
18. The memory interface of claim 17 , wherein the signal on the only one more memory interface contact is a bidirectional data strobe signal.
19. The memory interface of claim 18 , wherein the control circuitry uses a state of a signal line used to enable reading in the asynchronous operating mode to control direction of data and the bidirectional data strobe signal.