Semiconductor packages having warpage compensation
A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.
1. A semiconductor device comprising:
a semiconductor package comprising a substrate body comprising a first surface and a second surface, a semiconductor chip mounted on the first surface, and a plurality of first electrode pads formed on the second surface;
a plurality of external contact electrodes respectively formed on the first electrode pads; and
a mother board comprising a plurality of second electrode pads respectively electrically connected to the external contact electrodes,
wherein at least one selected from the group consisting of heights of the external contact electrodes and pitches between the first electrode pads are determined to be different from each other according to a warpage direction of the semiconductor package in a soldering temperature range near a melting point of the external contact electrodes in a heat treatment process for forming the external contact electrodes.
2. The semiconductor device of claim 1 , wherein at least one selected from the group consisting of sizes of the first electrode pads and volumes of the external contact electrodes are determined to be different from each other according to the warpage direction of the semiconductor package in the soldering temperature range, and correspondingly, the heights of the external contact electrodes are determined to be different from each other.
3. The semiconductor device of claim 1 , wherein sizes of the second electrode pads are determined to be different from each other, corresponding to at least one selected from the group consisting of volumes of the external contact electrodes corresponding to the second electrode pads and sizes of the first electrode pads corresponding to the second electrode pads.
4. The semiconductor device of claim 1 , wherein pitches between the second electrode pads are determined to be different from each other, corresponding to pitches of the first electrode pads corresponding to the second electrode pads.
5. The semiconductor device of claim 1 , wherein the semiconductor package has a positive, that is, concave warpage in the soldering temperature range.
6. The semiconductor device of claim 5 , wherein pitches between the first electrode pads are narrowed in a direction away from the center of the second surface.
7. The semiconductor device of claim 5 , wherein pitches of the first electrode pads formed in a central region of the second surface are wider than pitches of the first electrode pads formed in an edge region of the second surface.
8. The semiconductor device of claim 7 , wherein the pitches of the first electrode pads formed in the central region of the second surface are identical to each other, and the pitches of the first electrode pads formed in the edge region of the second surface are identical to each other.
9. The semiconductor device of claim 5 , wherein pitches of the first electrode pads formed in a central region of the second surface are narrowed in a direction away from the center of the second surface, and pitches of the first electrode pads formed in an edge region of the second surface are identical to each other.
10. The semiconductor device of claim 5 , wherein heights of the external contact electrodes formed in a central region of the second surface are smaller than heights of the external contact electrodes formed in an edge region of the second surface.
11. The semiconductor device of claim 10 , wherein sizes of the first electrode pads formed in the central region of the second surface are greater than sizes of the first electrode pads formed in the edge region of the second surface.
12. The semiconductor device of claim 10 , wherein at least one of the first electrode pads formed in the central region of the second surface is a dummy pad.
13. The semiconductor device of claim 10 , wherein volumes of the external contact electrodes formed in the central region of the second surface are smaller than volumes of the external contact electrodes formed in the edge region of the second surface.
14. The semiconductor device of claim 1 , further comprising a top semiconductor package stacked on the semiconductor package.
15. A semiconductor package comprising:
a substrate body having a first surface and a second surface;
a semiconductor chip mounted on the first surface, and
a plurality of electrode pads on the second surface selectively formed to have progressively smaller sizes from a central region of the substrate body toward an outer edge of the substrate body based on a first reflow soldering process warpage profile for the semiconductor package and formed to have progressively larger sizes extending from the central region of the substrate body toward the outer edge of the substrate body based on a second reflow soldering process warpage profile for the semiconductor package.
16. The semiconductor package of claim 15 , further comprising:
a motherboard having the substrate body mounted thereon, including external contact electrodes electrically coupled to respective ones of the pluralities of electrode pads, wherein external contact electrodes have sizes that progressively increase or decrease from the central portion towards the outer edge.
17. The semiconductor package of claim 16 , wherein the semiconductor package has a first warpage at a reflow temperature and the motherboard has a second warpage that is opposite the first warpage at the reflow temperature.