Three dimensional stacked chip package structure
This disclosure related to a stacked chip package structure having a sloped dam structure located on the substrate and beside the chip stack. The dam structure can facilitate the dispensing process of the underfill.
1. A stacked chip package structure, comprising:
at least a chip stack disposed on a substrate, wherein the chip stack includes at least two chips piled up over the substrate in a first direction;
a dam structure disposed on the substrate, wherein the dam structure leans against at least one side of the chip stack, the dam structure has at least one slanted surface extending aslant along the at least one side of the chip stack and from a middle or higher of the chip stack to the substrate; and
an underfill filled between the chips of the chip stack.
2. The stacked chip package structure of claim 1 , wherein the dam structure is a triangular prism having a side surface in a right-triangle shape and a slanted surface.
3. The stacked chip package structure of claim 1 , wherein the dam structure is a triangular prism having a side surface in an isosceles-triangle shape and a slanted surface.
4. The stacked chip package structure of claim 1 , wherein the dam structure includes a trapezoid cuboid and a triangular prism connected to the trapezoid cuboid, the trapezoid cuboid leans against one side of the chip stack and has a first slanted surface, the triangular prism leans against another side of the chip stack and has a second slanted surface connected to the first slanted surface, the connected first and second slanted surfaces extend aslant over two adjacent sides of the chip stack and extend from a middle or higher of the chip stack to the substrate.
5. The stacked chip package structure of claim 1 , wherein the dam structure includes a first triangular prism and a second triangular prism, the first triangular prism leans against one side of the chip stack and has a first slanted surface, the second triangular prism leans against another side of the chip stack and has a second slanted surface, the first slanted surface extends aslant from a middle or higher of the chip stack to the substrate at one side, and the second slanted surface extends aslant from the middle of the chip stack to the substrate at another side.
6. The stacked chip package structure of claim 1 , wherein the dam structure is located between two chip stacks and leans against both chip stacks.
7. The stacked chip package structure of claim 1 , wherein the substrate is a semiconductor substrate, an interposer or a printed circuit board.
8. The stacked chip package structure of claim 1 , wherein a material of the dam structure includes a high thixotropic material having a viscosity ranging between 100,000 cps˜1,300,000 cps and higher than a viscosity of the underfill.
9. The stacked chip package structure of claim 1 , wherein the dam structure includes a stepped slope.
10. The stacked chip package structure of claim 1 , wherein the chip is a thinned chip, a memory chip or a high-frequency chip.
11. The stacked chip package structure of claim 1 , wherein the chip stack includes at least two chips electrically connected to the substrate by flip chip bonding.
12. The stacked chip package structure of claim 1 , wherein the dam structure extends from a top layer of the chip stack to the substrate.