Disturb verify for programming memory cells
Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.
1. A method for programming memory cells, comprising:
applying a number of programming pulses to a first memory cell;
performing a disturb verify operation to determine whether a second memory cell adjacent to the first memory cell exceeds an uppermost acceptable level for a data state of the second memory cell; and
inhibiting the first memory cell from programming in response to the second memory cell failing the disturb verify operation.
2. The method of claim 1 , wherein the method includes enabling programming of the first memory cell in response to the second memory cell passing the disturb verify operation.
3. The method of claim 1 , wherein performing the disturb verify operation on a second memory cell adjacent to the first memory cell comprises performing the disturb verify operation on the second memory cell if the second memory cell is in a lowermost data state of a number of data states and a target data state of the first memory cell is an uppermost data state of the number of data states.
4. The method of claim 3 , wherein applying a number of programming pulses to a first memory cell comprises applying the number of programming pulses to the first memory cell and a third memory cell adjacent to the second memory cell, and performing a disturb verify operation on a second memory cell adjacent to the first memory cell comprises performing the disturb verify operation on the second memory cell if the second memory cell is in an erased state and a target data state of the first memory cell and the third memory cell is an uppermost data state of a number of data states.
5. The method of claim 1 , wherein performing a disturb verify operation includes determining whether a threshold voltage of the second memory cell exceeds a particular threshold corresponding to a target data state of the second memory cell.
6. A method for programming memory cells, comprising:
applying a number of programming pulses to a first memory cell and a third memory cell that are adjacent to a second memory cell;
performing a disturb verify operation to determine whether the second memory cell exceeds an uppermost acceptable level for a data state of the second memory cell;
inhibiting at least one of the first and the third memory cells from further programming in response to the second memory cell failing the disturb verify operation.
7. The method of claim 6 , wherein the method includes selectively disabling the disturb verify operation.
8. The method of claim 6 , wherein the method includes applying an additional programming pulse to the first and the third memory cells after performing the disturb verify operation.
9. The method of claim 6 , wherein inhibiting at least one of the first and the third memory cells from further programming comprises inhibiting both of the first and the third memory cells from further programming.
10. The method of claim 6 , wherein inhibiting at least one of the first and the third memory cells from further programming comprises inhibiting only one of the first and the third memory cells from further programming.
11. An apparatus, comprising:
an array of memory cells; and
control circuitry coupled to the array, wherein the control circuitry is configured to:
apply a number of programming pulses to a first memory cell of the array and a third memory cell of the array, wherein the first and the second memory cells are adjacent to a second memory cell of the array;
perform a disturb verify operation to determine whether the second memory cell exceeds an uppermost acceptable level for a data state of the second memory cell;
inhibit at least one of the first and the third memory cells from further programming in response to the second memory cell failing the disturb verify operation.
12. The apparatus of claim 11 , wherein the control circuitry being configured to perform a disturb verify operation on the second memory cell comprises the control circuitry being configured to perform the disturb verify operation on the second memory cell if the first and the third memory cells have a target data state of an uppermost data state of a number of data states.
13. The apparatus of claim 11 , wherein the control circuitry is configured to perform the disturb verify operation by applying a sensing voltage to the second memory cell, wherein the sensing voltage is greater than an uppermost voltage associated with an erased state.
14. The apparatus of claim 13 , wherein teh sensing voltage is negative.
15. The apparatus of claim 11 , further including a host coupled to the control circuitry.