Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows
A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.
1. A debugging circuit that receives arithmetic operation data for causing an arithmetic unit provided within a processor to perform an arithmetic operation, and a control signal used for the arithmetic operation, the debugging circuit comprising:
a counter that counts cyclically in response to an internal clock of the processor and outputs a counter value;
an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal; and
a debug storage unit that stores the arithmetic operation data, the counter value, and the control signal when the output signal of the OR circuit is valid, wherein the control signal indicates whether or not the arithmetic operation data is valid.
2. The debugging circuit according to claim 1 , wherein
said counter signal that is output when the counter value of said counter is the specific value is an overflow signal output from the counter.
3. The debugging circuit according to claim 1 , wherein
said counter signal that is output when the counter value of said counter is the specific value is the output of a comparator receiving inputs of a counter value output from the counter and said specific value.
4. The debugging circuit according to claim 1 , wherein
said counter outputs the counter value when the control signal is valid.
5. The debugging circuit according to claim 1 , wherein
said counter operates synchronously with said arithmetic operation, or operates when the control signal is valid, in accordance with an externally input mode signal.
6. The debugging circuit according to claim 1 , wherein
the counter outputs the counter value synchronously with the arithmetic operation.
7. A processor comprising:
a data control unit that provides arithmetic operation data;
an arithmetic control unit that outputs a control signal and the arithmetic operation data;
an instruction control unit that controls the arithmetic control unit;
an arithmetic unit that executes a prescribed arithmetic operation using the control signal and the arithmetic operation data;
a counter that counts cyclically in response to an internal clock of the processor and outputs a counter value;
an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal; and
a debug storage unit that stores the arithmetic operation data, the counter value, and the control signal when the output signal of the OR circuit is valid, wherein the control signal indicates whether or not the arithmetic operation data is valid.