Method of eliminating a lithography operation
Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.
1. A computer program product comprising a non-transitory computer useable medium having computer program code embodied therein for enabling a computing device to generate datasets for photolithography operations, the code comprising instructions for:
receiving a layout dataset representing features of a circuit;
deriving a first dataset representing lines and connection features within the layout dataset;
generating a first mask dataset from the first dataset, wherein the first mask dataset represents a first pattern comprising a first set of lines and a second set of lines, wherein the first set of lines and the second set of lines define wide spaces and narrow spaces, and wherein, during a spacer-etch process, the wide spaces define parallel line features such that spacer material remains closely adjacent to vertical surfaces and there is a space between adjacent spacers, and the narrow spaces define connection features such that spacer material remains within the narrow spaces, wherein the spacer material adjacent to each of the vertical surfaces of one of the narrow spaces is connected such that that narrow space is completely covered by spacer material; and
generating a second mask dataset, wherein the second mask dataset represents a second pattern comprising portions of the spacer material to be further etched in order to trim the first pattern.
2. The computer program product of claim 1 , wherein the first set of lines defines a first set of parallel line features and the second set of lines defines a second set of parallel line features.
3. The computer program product of claim 2 , wherein the first set of lines and the second set of lines are aligned with respect to each other.
4. The computer program product of claim 3 , wherein the first set of parallel line features, the second set of parallel line features, and a connection feature form an H-shape feature pattern.
5. The computer program product of claim 2 , wherein the first set of lines and the second set of lines are staggered with respect to each other.
6. The computer program product of claim 5 , wherein the first set of parallel spacer features, the second set of parallel spacer features, and a connection feature form a herringbone shape.
7. A computer-aided design tool, comprising:
a processor, and
a memory, coupled to the processor and having computer program code embodied therein for enabling the processor to generate datasets for photolithography operations, the code comprising instructions for:
receiving a layout dataset representing features of a circuit;
deriving a first dataset representing lines and connection features within the layout dataset;
generating a first mask dataset from the first dataset, wherein the first mask dataset represents a first pattern comprising a first set of lines and a second set of lines, wherein the first set of lines and the second set of lines define wide spaces and narrow spaces, and wherein, during a spacer-etch process, the wide spaces define parallel line features such that spacer material remains closely adjacent to vertical surfaces and there is a space between adjacent spacers, and the narrow spaces define connection features such that spacer material remains within the narrow spaces, wherein the spacer material adjacent to each of the vertical surfaces of one of the narrow spaces is connected such that that narrow space is completely covered by spacer material; and generating a second mask dataset, wherein the second mask dataset represents a second pattern comprising portions of the spacer material to be further etched in order to trim the first pattern.
8. The computer-aided design tool of claim 7 , wherein the first set of lines defines a first set of parallel line features and the second set of lines defines a second set of parallel line features.
9. The computer-aided design tool of claim 8 , wherein the first set of lines and the second set of lines are aligned with respect to each other.
10. The computer-aided design tool of claim 9 , wherein the first set of parallel line features, the second set of parallel line features, and a connection feature form an H-shape feature pattern.
11. The computer-aided design tool of claim 8 , wherein the first set of lines and the second set of lines are staggered with respect to each other.
12. The computer-aided design tool of claim 11 , wherein the first set of parallel spacer features, the second set of parallel spacer features, and a connection feature form a herringbone shape.