Ultra-low power multi-threshold asynchronous circuit design
View Patent ↗A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to V cc , and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.
1. A multi-threshold null convention logic circuit, the circuit comprising:
a first circuit;
a first high-threshold transistor coupled to V cc ; and
an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output;
wherein the set circuit is isolated from ground during a sleep cycle.
2. The circuit of claim 1 , wherein the first high-threshold transistor is driven by a sleep signal.
3. The circuit of claim 1 , wherein a second high-threshold transistor couples the first circuit to ground and is driven by a sleep signal.
4. The circuit of claim 1 , wherein a first low-threshold transistor couples the inverter output to ground and is driven by a sleep signal.
5. The circuit of claim 1 , wherein the output is driven to ground during a sleep cycle.
6. The circuit of claim 1 , wherein the first circuit includes a hold 0 circuit and a set circuit coupled together.
7. The circuit of claim 1 , wherein the first circuit drives the inverter with a logic 1 during a sleep mode following assertion of the sleep signal.
8. The circuit of claim 7 , wherein isolating the inverter from Vcc and driving the inverter with a logic 1 during the sleep cycle prevents a glitch upon exiting the sleep cycle 10 .
9. The circuit of claim 1 , wherein the inverter is isolated from Vcc during a sleep cycle.
10. The circuit of claim 1 , wherein the first circuit is coupled to Vcc exclusively by one or more high-threshold transistors.
11. A multi-threshold null convention logic circuit, the circuit comprising:
an inverter coupled to ground and having an output;
a first circuit driving the inverter; and
a high-threshold transistor driven by a sleep signal having an asserted and a non-asserted state, and coupling the inverter to Vcc when the sleep signal is in the non-asserted state and isolating the inverter from Vcc when the sleep signal is in the asserted state, and
a second high-threshold transistor driven by a second sleep signal having a second asserted stated and a second non-asserted state, the second high-threshold transistor coupling the first circuit to ground when the second sleep signal is in the second asserted state and isolating the first circuit from ground when the second sleep signal is in the second non-asserted state;
wherein the first circuit drives the inverter with a logic 1 during a sleep mode following assertion of the sleep signal;
wherein a glitch on the output when the sleep signal switches from the asserted state to the non-asserted state is prevented.
12. The circuit of claim 11 , wherein the first circuit includes a plurality of high-threshold transistors and low-threshold transistors, the first circuit coupled to Vcc by only high-threshold transistors.
13. The circuit of claim 11 , wherein the second signal is in the second non-asserted state when the sleep signal is in the asserted state and is in the second asserted state when the sleep signal is in the non-asserted state.
14. A method of manufacturing a logic circuit having an output and receiving a sleep signal having an asserted state and a non-asserted state, the method comprising:
providing a first circuit for performing the logic, the first circuit coupled to Vcc by one or more high-threshold transistors, the first circuit having a second output;
providing an inverter driven by the second output, the inverter driving the output; and
providing a sleep circuit to couple and isolate the inverter to Vcc and the first circuit to ground based on the state of the sleep signal; and
isolating the first circuit from ground via the high-threshold transistor of the sleep circuit when the sleep signal is in the asserted state.
15. The method of claim 14 , further comprising coupling the inverter to Vcc via a high-threshold transistor of the sleep circuit when the sleep signal is in the non-asserted state.
16. The method of claim 14 , further comprising isolating the inverter from Vcc via the high-threshold transistor of the sleep circuit when the sleep signal is in the asserted state.
17. The method of claim 14 , further comprising coupling the first circuit to ground via a high-threshold transistor of the sleep circuit when the sleep signal is in the non-asserted state.
18. The method of claim 14 , further comprising coupling the output to ground via a low-threshold transistor when the sleep signal is in the asserted state.
19. The method of claim 14 , wherein the logic circuit is a threshold gate.