Method for self-aligned doubled patterning lithography
Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
1. A method of semiconductor device fabrication for patterning a target layout of line features and large features comprising:
depositing a first layer of a first material and patterning the first layer to form a first pattern on a substrate, wherein the first pattern comprises first array of line features;
depositing a spacer material over the first pattern on the substrate;
etching the spacer material such that spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern;
removing the first pattern from the substrate;
selectively removing the spacer material, such that the spacer material that remains forms a spacer material pattern comprising the line features of the target layout; and
depositing a second layer of a second material over the spacer material pattern and patterning the second layer to form a second pattern, wherein the second pattern is different from the first pattern and comprises the larger features of the target layout.
2. The method of claim 1 , wherein the target layout has a density of line features double that of the first array.
3. The method of claim 1 , wherein the line features within the target layout are narrower than a minimum critical dimension that can be produced with a photolithographic patterning process.
4. The method of claim 3 , wherein the large features of the target layout are wider than the minimum critical dimension that can be produced with a photolithographic process.
5. The method of claim 1 , wherein the first layer and second layer combined from a gate of the circuit design.
6. The method of claim 1 , wherein the large features of the target layout include connections features, pad features and logic devices.
7. The method of claim 1 , wherein depositing and patterning the second layer occurs after depositing the spacer material and before etching the spacer material.
8. The method of claim 1 , wherein depositing and patterning the second layer occurs after removing the first pattern from the substrate.
9. The method of claim 1 , wherein selectively removing the spacer material involves using a photomask to remove certain portions of the spacer material.
10. The method of claim 1 , wherein patterning the first layer and the second layer involves using a photomask.