Method for fabricating magnetic tunnel junction

1. A method for fabricating a magnetic tunnel junction element, comprising:

forming a magneto resistance layer including a first magnetic layer, an insulation layer and a second magnetic layer on a substrate;

forming a magnetic loss area by doping a magnetic loss impurity into a region of the magneto resistance layer to cause a magnetic loss; and

etching the magnetic loss area to form a magnetic tunnel junction element.

2. The method of claim 1 , further comprising forming a hard mask layer and a mask pattern on the magneto resistance layer after forming the magneto resistance layer.

3. The method of claim 2 , wherein the forming of the magnetic loss area comprises doping the magnetic loss impurity into the magneto resistance layer using the mask pattern as an etching mask.

4. The method of claim 2 , wherein the etching of the magnetic loss area is performed using the mask pattern as an etch barrier.

5. The method of claim 1 , wherein the magnetic loss impurity includes at least one selected from the group consisting of Ga, Ge, As and In.

6. The method of claim 1 , wherein the first magnetic layer comprises a pinning layer including at least one selected from the group consisting of IrMn, PtMn, MnO, MnS, MnTe, MnF 2 , FeF 2 , FeCl 2 , FeO, CoCl 2 , CoO, NiCl 2 and NiO, and a pinned layer including at least one selected from the group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO 2 , MnOFe 2 O 3 , FeOFe 2 O 3 , NiOFe 2 O 3 , CuOFe 2 O 3 , EuO and Y 3 Fe 5 O 12 .

7. The method of claim 1 , wherein the second magnetic layer includes at least one selected from the group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO 2 , MnOFe 2 O 3 , FeOFe 2 O 3 , NiOFe 2 O 3 , CuOFe 2 O 3 , EuO and Y 3 Fe 5 O 12 .

8. The method of claim 1 , further comprising:

forming a capping layer to surround the magnetic tunnel junction element; and

oxidizing the capping layer.

9. The method of claim 8 , wherein the capping layer includes at least one selected from the group consisting of Al, Cr and Ta.

10. A semiconductor device including a magnetic tunnel junction element, comprising:

a patterned magneto resistance layer; and

an electrode layer on the patterned magneto resistance layer wherein the patterned magneto resistance layer includes a magnetic loss area formed by doping a magnetic loss impurity except for a region for maintaining magnetic properties, wherein the magnetic loss impurity causes a magnetic loss.

11. The semiconductor device of claim 10 , wherein the magnetic loss impurity includes at least one selected from the group consisting of Ga, Ge, As and In.

12. The semiconductor device of claim 10 , wherein the patterned magneto resistance layer includes a first magnetic layer, an insulation layer and a second magnetic layer.

13. The semiconductor device of claim 12 , wherein the first magnetic layer comprises a pinning layer including at least one selected from the group consisting of IrMn, PtMn, MnO, MnS, MnTe, MnF 2 , FeF 2 , FeCl 2 , FeO, CoCl 2 , CoO, NiCl 2 and NiO, and a pinned layer including at least one selected from the group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO 2 , MnOFe 2 O 3 , FeOFe 2 O 3 , NiOFe 2 O 3 , CuOFe 2 O 3 , EuO and Y 3 Fe 5 O 12 .

14. The semiconductor device of claim 13 , wherein the second magnetic layer includes at least one selected from the group consisting of Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO 2 , MnOFe 2 O 3 , FeOFe 2 O 3 , NiOFe 2 O 3 , CuOFe 2 O 3 , EuO and Y 3 Fe 5 O 12 .

15. The semiconductor device of claim 10 , further comprising a capping layer that surrounds the patterned magneto resistance layer and the electrode layer.

16. The method of claim 15 , wherein the capping layer including at least one selected from the group consisting of Al, Cr and Ta.