Silicon carbide semiconductor device

1. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide having a hexagonal crystal structure and having a main surface;

a silicon carbide layer epitaxially formed on said main surface of said substrate, said silicon carbide layer being provided with a trench having a side wall inclined relative to said main surface, said side wall having an off angle of not less than 50° and not more than 65° relative to a {0001} plane;

a gate insulating film provided on said side wall of said silicon carbide layer; and

a gate electrode provided on said gate insulating film, said silicon carbide layer including a body region having a first conductivity type and facing said gate electrode with said gate insulating film being interposed therebetween, a channel region formed at a surface of said body region along said side wall, and a pair of regions separated from each other by said body region and having a second conductivity type, said body region having an impurity density of 5×10 16 cm −3 or greater such that said gate electrode has a threshold voltage which allows a weak inversion layer to be formed in said body region, said threshold voltage being 2 V or greater in a temperature range of not less than a room temperature and not more than 100° C. and such that channel mobility of electrons is 30 cm 2 /Vs or greater at the room temperature.

2. The silicon carbide semiconductor device according to claim 1 , wherein said side wall has an off orientation forming an angle of 5° or smaller relative to a <01-10> direction.

3. The silicon carbide semiconductor device according to claim 2 , wherein said side wall has an off angle of not less than −3° and not more than 5° relative to a {03-38} plane relative to the <01-10> direction.

4. The silicon carbide semiconductor device according to claim 1 , wherein said side wall corresponds to a plane of a carbon plane side of the silicon carbide constituting said substrate.

5. The silicon carbide semiconductor device according to claim 1 , wherein said body region has an impurity density of 1×10 20 cm −3 or smaller.

6. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device is a normally-off type.

7. The silicon carbide semiconductor device according to claim 6 , wherein said gate electrode is made of polysilicon having said first conductivity type.

8. The silicon carbide semiconductor device according to claim 1 , wherein said gate electrode is made of n type polysilicon.

9. The silicon carbide semiconductor device according to claim 1 , wherein said gate insulating film has a thickness of not less than 25 nm and not more than 70 nm.

10. The silicon carbide semiconductor device according to claim 1 , wherein said first conductivity type is p type and said second conductivity type is n type.

11. The silicon carbide semiconductor device according to claim 10 , wherein said body region has an impurity density of not less than 8×10 16 cm −3 and not more than 3×10 18 cm −3 .

12. The silicon carbide semiconductor device according to claim 1 , wherein said threshold voltage is 3 V or greater at 100° C.

13. The silicon carbide semiconductor device according to claim 1 , wherein said threshold voltage is 1 V or greater at 200° C.

14. The silicon carbide semiconductor device according to claim 1 , wherein said threshold voltage has a temperature dependency of −10 mV/° C. or greater.

15. The silicon carbide semiconductor device according to claim 1 , wherein the channel mobility of electrons is 50 cm 2 /Vs or greater at 100° C.

16. The silicon carbide semiconductor device according to claim 1 , wherein the channel mobility of electrons is 40 cm 2 /Vs or greater at 150° C.

17. The silicon carbide semiconductor device according to claim 1 , wherein the channel mobility of electrons has a temperature dependency of −0.3 cm 2 /Vs° C. or greater.

18. The silicon carbide semiconductor device according to 1 , wherein a barrier height at an interface between said silicon carbide layer and said gate insulating film is not less than 2.2 eV and not more than 2.6 eV.

19. The silicon carbide semiconductor device according to 1 , wherein:

said pair of regions include a breakdown voltage holding layer ( 2 ) separating said body region and said substrate from each other, and

in an ON state, a channel resistance, which is a resistance value of a channel region formed in said body region, is smaller than a drift resistance, which is a resistance value in said breakdown voltage holding layer.

20. The silicon carbide semiconductor device according to 1 , wherein the silicon carbide semiconductor device is a vertical type insulated gate field effect transistor.

21. The silicon carbide semiconductor device according to 1 , wherein said side wall is formed through thermal etching.

22. The silicon carbide semiconductor device according to 1 , further comprising two or more sets of said side walls facing each other, wherein

each of said two or more sets of side walls facing each other has an off angle of not less than 50° and not more than 65° relative to the {0001} plane.

23. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide having a hexagonal crystal structure and having a main surface;

a silicon carbide layer epitaxially formed on said main surface of said substrate, said silicon carbide layer being provided with a trench having first to sixth side walls inclined relative to said main surface, said first to sixth side walls being formed of a (03-3-8) plane, a (−303-8) plane, a (3-30-8) plane, a (0-33-8) plane, a (30-3-8) plane, and a (−330-8) plane, each of which has an off angle of not less than −3° and not more than 5° relative to a <01-10> direction;

a gate insulating film provided on said first to sixth side walls of said silicon carbide layer; and

a gate electrode provided on said gate insulating film, said silicon carbide layer including a body region having a first conductivity type and facing said gate electrode with said gate insulating film being interposed therebetween, a channel region formed at a surface of said body region along said first to sixth side walls, and a pair of regions separated from each other by said body region and having a second conductivity type, said body region having an impurity density of 5×10 16 cm −3 or greater.

24. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide having a hexagonal crystal structure and having a main surface;

a silicon carbide layer epitaxially formed on said main surface of said substrate, said silicon carbide layer being provided with a trench having first and second side walls adjacent to each other and inclined relative to said main surface, each of said first and second side walls having an off angle of not less than 50° and not more than 65° relative to a {0001} plane;

a gate insulating film provided on said first and second side walls of said silicon carbide layer; and

a gate electrode provided on said gate insulating film, said silicon carbide layer including a body region having a first conductivity type and facing said gate electrode with said gate insulating film being interposed therebetween, a channel region formed at a surface of said body region along said first and second side walls, and a pair of regions separated from each other by said body region and having a second conductivity type, said body region having an impurity density of 5×10 16 cm −3 or greater.