Metal structure for memory device
View Patent ↗A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.
1. A method comprising:
forming a memory unit cell in a substrate;
forming a first metal layer over the substrate, the first metal layer providing local interconnection to the memory unit cell;
forming a second metal layer over the first metal layer, the second metal layer including a first bit line and a second bit line each having a first thickness; and
forming a third metal layer over the second metal layer, the third metal layer including a word line and a first Vss line, wherein the word line has a second thickness greater than the first thickness, wherein the Vss line continuously extends parallel to the word line from at least the first bit line to at least the second bit line.
2. The method of claim 1 , wherein the second metal layer further includes a power supply line disposed between the first and second bit lines.
3. The method of claim 1 , wherein a length ratio of the word line to the first bit line is greater than about 2.0 in the memory unit cell.
4. The method of claim 1 , wherein the first bit line has a first resistance and the word line has a second resistance that is less than the first resistance.
5. The method of claim 1 , further comprising forming a fourth metal layer over the third metal layer, wherein the fourth metal layer includes a second Vss line electrically coupled to the first Vss line.
6. The method of claim 5 , wherein the first Vss line runs perpendicular to the second Vss line.
7. The method of claim 1 , wherein the second metal layer has a greater thickness than the first metal layer.
8. A method comprising:
forming a first metal layer over the substrate, the first metal layer providing local interconnection to a memory unit cell;
forming a second metal layer over the first metal layer, the second metal layer including a bit line, a complementary bit line, and a Vcc line disposed between the bit line and the complementary bit line, the bit line and the complementary bit line each having a first thickness;
forming a third metal layer over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness, wherein the third metal layer further includes a first Vss line that continuously extends parallel with the word line from at least the complementary bit line to at least the bit line; and
forming a fourth metal layer over the third metal layer.
9. The method of claim 8 , wherein the fourth metal layer includes a second Vss line electrically coupled to the first Vss line, the second Vss line perpendicular to the first Vss line.
10. The method of claim 8 , wherein the memory unit cell includes a SRAM memory unit cell.
11. The method of claim 8 , wherein the second metal layer has a greater thickness than the first metal layer, and
wherein the fourth metal layer has a greater thickness than the third metal layer.
12. The method of claim 8 , wherein the bit line has a first resistance and the word line has a second resistance that is less than the first resistance.
13. The method of claim 8 , wherein the third metal layer further includes a second Vss line that continuously extends parallel with the word line from at least the complementary bit line to at least the bit line.
14. The method of claim 13 , wherein the word line is disposed between the first and second Vss lines.
15. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming an SRAM unit cell in the substrate;
forming a first metal layer over the substrate, the first metal layer providing local interconnection to the SRAM unit cell;
forming a second metal layer over the first metal layer, the second metal layer including a bit line, a complementary bit line, and a Vcc line disposed between the bit line and the complementary bit line, the bit line and the complementary bit line each having a first thickness; and
forming a third metal layer over the second metal layer, the third metal layer including a word line having a second thickness less than the first thickness.
16. The method of claim 15 , wherein a thickness ratio of the second thickness to the first thickness is greater than 1.05.
17. The method of claim 15 , wherein the third metal layer further includes a first Vss line that is parallel with the word line.
18. The method of claim 17 , further comprising forming a fourth metal layer over the third metal layer, the fourth metal layer including a second Vss line electrically coupled to the first Vss line, the second Vss line perpendicular to the first Vss line.
19. The method of claim 15 , wherein the third metal layer further includes a first Vss line that continuously runs parallel with the word line from at least the bit line to at least the complementary bit line.
20. The method of claim 15 , wherein a length ratio of the word line to the bit line is greater than about 2.0 in the memory unit cell.