Very extremely thin semiconductor package
A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package.
1. A package comprising:
a. a first semiconductor die;
b. a formed lead frame having a plurality of formed leads each having a first end positioned near but spaced apart from the first semiconductor die and substantially in a first planar level, a second end substantially in the first planar level, and a middle section between the first end and the second end, wherein the middle section is substantially in a second planar level, wherein the second planar level is higher than the first planar level, wherein the second end is exposed to an edge of the package on a bottom and but not a top of the package;
c. means for electrically coupling between at least one pad on the first semiconductor die and at least one of the first ends;
d. a second semiconductor die stacked on and electrically insulated from the first semiconductor die wherein the second semiconductor die is electrically coupled to the at least one of the formed leads; and
e. a resin formed around the first semiconductor die and between the leads such that the package has a thickness substantially equal to a thickness of the lead frame.
2. The package according to claim 1 , wherein the lead frame and the package have a thickness in the range of 127 to 500 micro meters.
3. The package according to claim 1 , wherein the second planar level is higher than the first planar level by an amount no more than an amount greater than a thickness of the first semiconductor die.
4. The package according to claim 1 , wherein the second planar level is higher than the first planar level by at least a thickness of the first semiconductor die.
5. The package according to claim 1 , wherein a back side of the semiconductor die is exposed between the first ends and the means for electrically coupling comprises wire bonds.
6. The package according to claim 1 , further comprising a system formed by stacking at least two packages, such that the leads of one package are positioned adjacent to and are electrically coupled with the leads of the other package.
7. The package according to claim 1 , further comprising a plated surface on the leads to enhance bonding.
8. The package according to claim 1 , further comprising a plated surface on the lead frame to enhance board soldering.
9. The package according to claim 1 , wherein the first and second planar levels are electrically exposed to an exterior surface of the package.
10. The package according to claim 1 , wherein one or more bond wires electrically coupling the first semiconductor die to one or more of the formed leads have at least one bend forming a corner for minimizing the distance the one or more bond wires extend above the top of the first semiconductor die.
11. The package according to claim 1 , further comprising molding at top corners for anchoring the lead frame within the resin.
12. The package according to claim 1 , further comprising means for electrically coupling between at least one pad on the second semiconductor die and at least one of the first ends.