IP Library Granted Patent US 8,716,828
Granted Patent B2
US 8,716,828 · App. 13/473,175 · Granted May 6, 2014

Semiconductor device with isolation trench liner

Inventors: Richard J. Carter (Hopewell Junction, NY); George J. Kluth (Hopewell Junction, NY); Michael J. Hargrove (Clinton Corners, NY)
Assignee: Advanced Micro Devices, Inc.
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Quick Facts
Patent No.
US 8,716,828
App. No.
13/473,175
Granted
May 6, 2014
Kind
B2
Abstract

A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Claims (37)

1. A semiconductor device comprising:

a layer of semiconductor material having an active transistor region defined therein;

an isolation trench formed in the layer of semiconductor material adjacent to the active transistor region;

a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench;

an insulating material in the lined trench; and

a high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, wherein the trench liner creates a discontinuity in the high-k gate material between a portion of the high-k gate material overlying the portion of the insulating material and a portion of the high-k gate material overlying the portion of the active transistor region.

2. The semiconductor device of claim 1 ,

wherein the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

3. The semiconductor device of claim 2 , wherein the trench liner forms an oxygen barrier between the high-k gate material overlying the portion of the insulating material and the high-k gate material overlying the portion of the active transistor region.

4. The semiconductor device of claim 2 , wherein:

the trench liner includes an upper rim; and

the upper rim is substantially void of the high-k gate material.

5. The semiconductor device of claim 2 , further comprising:

a metal gate layer overlying the high-k gate material and overlying the trench liner;

and a polysilicon gate layer overlying the metal gate layer.

6. The semiconductor device of claim 2 , wherein the trench liner is formed from a nitride material.

7. The semiconductor device of claim 2 , wherein the insulating material is an oxide material.

8. The semiconductor device of claim 1 , wherein the trench liner separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

9. The semiconductor device of claim 1 , wherein the trench liner forms an oxygen barrier between the high-k gate material overlying the portion of the insulating material and the high-k gate material overlying the portion of the active transistor region.

10. The semiconductor device of claim 1 , wherein:

the trench liner includes an upper rim; and

the upper rim is substantially void of the high-k gate material.

11. The semiconductor device of claim 1 , further comprising:

a metal gate layer overlying the high-k gate material and overlying the trench liner;

and a polysilicon gate layer overlying the metal gate layer.

12. The semiconductor device of claim 1 , wherein the trench liner is formed from a nitride material.

13. The semiconductor device of claim 1 ,

wherein the trench liner forms an oxygen barrier between the high-k gate material overlying the portion of the insulating material and the high-k gate material overlying the portion of the active transistor region.

14. The semiconductor device of claim 13 , wherein the trench liner separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

15. The semiconductor device of claim 2 , wherein the trench liner forms an oxygen barrier between the high-k gate material overlying the portion of the insulating material and the high-k gate material overlying the portion of the active transistor region.

16. The semiconductor device of claim 13 , wherein:

the trench liner includes an upper rim; and

the upper rim is substantially void of the high-k gate material.

17. The semiconductor device of claim 13 , further comprising:

a metal gate layer overlying the high-k gate material and overlying the trench liner;

and a polysilicon gate layer overlying the metal gate layer.

18. The semiconductor device of claim 13 , wherein the trench liner is formed from a nitride material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2016
From: ADVANCED MICRO DEVICES, INC.
To: CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
Reel/Frame 040879/0437 →
Continuity (3)
Division 13178362 · Jul 7, 2011
Division 12199616 · Aug 27, 2008
Related Publication 20120223399A1 · Sep 6, 2012