Analysis of compensated layout shapes
View Patent ↗The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.
1. A method for layout analysis, comprising:
analyzing, using at least one computing device, a semiconductor layout using a bucket structure, the layout including a semiconductor device;
applying a pattern template to the bucket structure; and
identifying a shape adjacent to the semiconductor device, in response to a plurality of rules included in the pattern template, wherein the plurality of rules includes:
determining whether an area of the adjacent shape within the bucket structure falls within predetermined minimum and maximum areas;
determining whether a location of the adjacent shape follows a predetermined pattern; and
determining whether an area of the adjacent shape is located on a predetermined level of the layout.
2. The method of claim 1 , further comprising:
computing stress effects for circuit simulation based on the identified adjacent shape.
3. The method of claim 1 , wherein the adjacent shape comprises:
a transistor including a gate having a compensated gate length.
4. The method of claim 1 , wherein the adjacent shape comprises:
a transistor including a gate having a compensated gate length, and wherein the predetermined minimum and maximum areas are indicative of a negative or positive compensation of the gate length, respectively.
5. The method of claim 1 , wherein the plurality of rules further includes:
determining whether a number of vertices of the adjacent shape within the bucket structure is greater than or equal to 8.
6. A system for layout analysis, comprising:
using at least one computing device for performing a method, the method comprising:
analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device;
applying a pattern template to the bucket structure; and
identifying a shape adjacent to the semiconductor device, in response to a plurality of rules included in the pattern template, wherein the plurality of rules includes:
determining whether an area of the adjacent shape within the bucket structure falls within predetermined minimum and maximum areas;
determining whether a location of the adjacent shape follows a predetermined pattern; and
determining whether an area of the adjacent shape is located on a predetermined level of the layout.
7. The system of claim 6 , wherein the method further comprises:
computing stress effects for circuit simulation based on the identified adjacent shape.
8. The system of claim 6 , wherein the adjacent shape comprises a transistor including a gate having a compensated gate length.
9. The system of claim 6 , wherein the plurality of rules further includes:
determining whether a number of vertices of the adjacent shape within the bucket structure is greater or equal to 8.
10. A computer program comprising program code embodied in at least one non-transient computer readable storage medium, which when executed, enables a computer system to implement a method for layout analysis, the method comprising:
analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device;
applying a pattern template to the bucket structure; and
identifying a shape adjacent to the semiconductor device, in response to a plurality of rules included in the pattern template, wherein the plurality of rules includes:
determining whether an area of the adjacent shape within the bucket structure falls within predetermined minimum and maximum areas;
determining whether a location of the adjacent shape follows a predetermined pattern;
determining whether an area of the adjacent shape is located on a predetermined level of the layout; and
computing stress effects for circuit simulation based on the identified adjacent shape.
11. The computer program of claim 10 , wherein the adjacent shape comprises a transistor including a gate having a compensated gate length.
12. The computer program of claim 10 , wherein the plurality of rules further includes:
determining whether a number of vertices of the adjacent shape within the bucket structure is greater or equal to 8.