IP Library Granted Patent US 8,748,943
Granted Patent B2
US 8,748,943 · App. 13/629,174 · Granted Jun 10, 2014

Bipolar junction transistor with stair profile

Inventor: Krister Gumaelius (Vaxholm, SE)
Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,748,943
App. No.
13/629,174
Granted
Jun 10, 2014
Kind
B2
Abstract

A semiconductor device and a method of forming a structure in a target substrate for manufacturing a semiconductor device is provided. The method comprises the step of providing a masking layer on the target substrate and providing a stair-like profile in the masking layer such that the height of a step of the stair-like profile is smaller than the thickness of the masking layer. Further, the method comprises the step of performing anisotropic etching of the masking layer and the target substrate simultaneously such that a structure having a stair-like profile is formed in the target substrate. The semiconductor device comprises a target substrate including a first region made of a first type of semiconductor material and a second region made of a second type of semiconductor material.

Claims (30)

1. A bipolar junction transistor, comprising:

a target substrate including a base region made of a first type of semiconductor material, the target substrate including a collector region and an emitter region made of a second type of semiconductor material different from the first type of semiconductor material,

the base region and the emitter region being adjacent and defining an active region of the bipolar junction transistor; and

a structure having a stair profile including a plurality of steps at a junction between the base region and the emitter region.

2. The bipolar junction transistor of claim 1 , wherein the base region includes a p-doped material and the emitter region includes an n-doped material, or vice versa.

3. The bipolar junction transistor of claim 1 , wherein a step from the plurality of steps of the stair profile defining a base of the structure includes a part of the base region and a part of the emitter region.

4. The bipolar junction transistor of claim 1 , wherein the target substrate includes at least one of silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), indium phosphide (InP) and gallium nitride (GaN).

5. The bipolar junction transistor of claim 1 , wherein a height of a step from the plurality of steps of the stair profile is less than 200 nm.

6. The bipolar junction transistor of claim 1 , wherein a number of steps included in the plurality of steps is greater than 4.

7. A bipolar junction transistor, comprising:

a target substrate including a base region made of a first type of semiconductor material, the target substrate including a collector region and an emitter region made of a second type of semiconductor material different from the first type of semiconductor material,

the base region and the emitter region being adjacent and defining an active region of the bipolar junction transistor; and

a structure having a stair profile at a junction between the base region and the emitter region, the stair profile having a first step and a second step, the first step defining a base of the structure, the first step including a part of the base region and a part of the emitter region.

8. The bipolar junction transistor of claim 7 , wherein the structure includes a side wall having a plurality of steps including at least the first step and the second step.

9. The bipolar junction transistor of claim 7 , wherein the structure includes more than one side wall having a plurality of steps.

10. The bipolar junction transistor of claim 7 , wherein the step of the stair profile has a height less than 100 nm.

11. The bipolar junction transistor of claim 7 , wherein the first step has a size different than a size of the second step.

12. The bipolar junction transistor of claim 7 , wherein first step of the stair profile has a width greater than a width of the second step of the stair profile, the second step of the stair profile is closer to a top of the structure than the first step of the stair profile.

13. The bipolar junction transistor of claim 7 , wherein first step of the stair profile has a height greater than a height of the second step of the stair profile, the second step of the stair profile is closer to a top of the structure than the first step of the stair profile.

14. The bipolar junction transistor of claim 7 , wherein the bipolar junction transistor is a vertical bipolar junction transistor.

15. The bipolar junction transistor of claim 7 , wherein the structure has a stair profile including more than two steps.

16. A bipolar junction transistor, comprising:

a base region made of a first type of semiconductor material;

a collector region made of a second type of semiconductor material different from the first type of semiconductor material;

an emitter region adjacent to the base region and made of the second type of semiconductor material, the emitter region and the base region defining at least a portion of an active region of the bipolar junction transistor; and

a structure having a stair profile including a plurality of steps at a junction between the base region and the emitter region.

17. The bipolar junction transistor of claim 16 , wherein a step from the plurality of steps of the stair profile includes a part of the base region and a part of the emitter region.

18. The bipolar junction transistor of claim 16 , wherein the bipolar junction transistor includes at least one of silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), indium phosphide (InP) and gallium nitride (GaN).

19. The bipolar junction transistor of claim 16 , wherein a height of a step from the plurality of steps of the stair profile is less than 200 nm.

20. The bipolar junction transistor of claim 16 , wherein the bipolar junction transistor is a vertical bipolar junction transistor.

Assignments (9)
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2013
From: TRANSIC AB
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 030615/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2013
From: GUMAELIUS, KRISTER
To: TRANSIC AB
Reel/Frame 030615/0869 →
Priority Claims (1)
SE 1050298 · Mar 30, 2010 · national
Continuity (3)
Continuation PCTEP2011054850 · Mar 29, 2011
Provisional Application 61319048 · Mar 30, 2010
Related Publication 20130020611A1 · Jan 24, 2013