IP Library › Granted Patent US 8,774,347
Granted Patent B2
US 8,774,347 · App. 13/675,077 · Granted Jul 8, 2014

Driver circuit, display device, and electronic device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,774,347
App. No.
13/675,077
Granted
Jul 8, 2014
Kind
B2
Abstract

To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11 , a transistor 12 , a transistor 13 , a transistor 14 , and a transistor 15 . When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Claims (71)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein each of the first to eighth transistors comprises a gate terminal, a source terminal, and a drain terminal,

wherein one of the source terminal and the drain terminal of the first transistor is electrically connected to one of the source terminal and the drain terminal of the second transistor, one of the source terminal and the drain terminal of the third transistor, one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,

wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the sixth transistor,

wherein one of the source terminal and the drain terminal of the fifth transistor is electrically connected to one of the source terminal and the drain terminal of the sixth transistor and is directly connected to one of the source terminal and the drain terminal of the seventh transistor,

wherein the gate terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,

wherein one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the fourth transistor,

wherein the other one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the fourth transistor, and

wherein the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the seventh transistor, and the one of the source terminal and the drain terminal of the seventh transistor are electrically isolated from each other.

2. The semiconductor device according to claim 1 ,

wherein one of the third transistor and the fourth transistor is in an Off state when the other of the third transistor and the fourth transistor is in an On state, and

wherein the fifth transistor is in an Off state when at least one of the second transistor, the third transistor, and the fourth transistor is in an On state.

3. The semiconductor device according to claim 1 , wherein all of the second transistor, the third transistor, and the fourth transistor are in an Off state when the first transistor is in an On state.

4. The semiconductor device according to claim 1 , wherein all the first to sixth transistors have the same conductivity type.

5. The semiconductor device according to claim 1 , further comprising a first capacitor and a second capacitor,

wherein the gate terminal of the third transistor is electrically connected to the first capacitor, and

wherein the gate terminal of the fourth transistor is electrically connected to the second capacitor.

6. The semiconductor device according to claim 1 , wherein the other of the source terminal and the drain terminal of the second transistor, the other of the source terminal and the drain terminal of the third transistor, and the other of the source terminal and the drain terminal of the fourth transistor are electrically connected to each other.

7. A display module comprising a pixel portion and a driver circuit configured to drive the pixel portion,

wherein the driver circuit includes the semiconductor device according to claim 1 .

8. The semiconductor device according to claim 1 , wherein the one of the source terminal and the drain terminal of the first transistor is directly connected to the one of the source terminal and the drain terminal of the second transistor, the one of the source terminal and the drain terminal of the third transistor, the one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,

wherein the gate terminal of the third transistor is directly connected to the gate terminal of the sixth transistor,

wherein one of the source terminal and the drain terminal of the fifth transistor is directly connected to one of the source terminal and the drain terminal of the sixth transistor,

wherein the gate terminal of the eighth transistor is directly connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,

wherein one of the source terminal and the drain terminal of the eighth transistor is directly connected to the gate terminal of the fourth transistor,

wherein the other one of the source terminal and the drain terminal of the eighth transistor is directly connected to the other one of the source terminal and the drain terminal of the fourth transistor.

9. The semiconductor device according to claim 1 , wherein the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the seventh transistor the gate terminal of the third transistor, the gate terminal of the eighth transistor, and the one of the source terminal and the drain terminal of the fifth transistor are electrically isolated from each other.

10. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein each of the first to eighth transistors comprises a gate terminal, a source terminal, and a drain terminal,

wherein one of the source terminal and the drain terminal of the first transistor is electrically connected to one of the source terminal and the drain terminal of the second transistor, one of the source terminal and the drain terminal of the third transistor, one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,

wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the sixth transistor,

wherein one of the source terminal and the drain terminal of the fifth transistor is electrically connected to one of the source terminal and the drain terminal of the sixth transistor and is directly connected to one of the source terminal and the drain terminal of the seventh transistor,

wherein the gate terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,

wherein one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal of the fourth transistor,

wherein the other one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the other one of the source terminal and the drain terminal of the fourth transistor,

wherein the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the seventh transistor, and the one of the source terminal and the drain terminal of the seventh transistor are electrically isolated from each other, and

wherein at least one of the first to eighth transistor comprises a channel formation region comprising an oxide semiconductor.

11. The semiconductor device according to claim 10 ,

wherein one of the third transistor and the fourth transistor is in an Off state when the other of the third transistor and the fourth transistor is in an On state, and

wherein the fifth transistor is in an Off state when at least one of the second transistor, the third transistor, and the fourth transistor is in an On state.

12. The semiconductor device according to claim 10 , wherein all of the second transistor, the third transistor, and the fourth transistor are in an Off state when the first transistor is in an On state.

13. The semiconductor device according to claim 10 , wherein all the first to seventh transistors have the same conductivity type.

14. The semiconductor device according to claim 10 , further comprising a first capacitor and a second capacitor,

wherein the gate terminal of the third transistor is electrically connected to the first capacitor, and

wherein the gate terminal of the fourth transistor is electrically connected to the second capacitor.

15. The semiconductor device according to claim 10 , wherein the other of the source terminal and the drain terminal of the second transistor, the other of the source terminal and the drain terminal of the third transistor, and the other of the source terminal and the drain terminal of the fourth transistor are electrically connected to each other.

16. A display module comprising a pixel portion and a driver circuit configured to drive the pixel portion,

wherein the driver circuit includes the semiconductor device according to claim 10 .

17. The semiconductor device according to claim 10 , wherein the one of the source terminal and the drain terminal of the first transistor is directly connected to the one of the source terminal and the drain terminal of the second transistor, the one of the source terminal and the drain terminal of the third transistor, the one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor,

wherein the gate terminal of the third transistor is directly connected to the gate terminal of the sixth transistor,

wherein one of the source terminal and the drain terminal of the fifth transistor is directly connected to one of the source terminal and the drain terminal of the sixth transistor,

wherein the gate terminal of the eighth transistor is directly connected to the other one of the source terminal and the drain terminal of the first transistor and the gate terminal of the first transistor,

wherein one of the source terminal and the drain terminal of the eighth transistor is directly connected to the gate terminal of the fourth transistor, and

wherein the other one of the source terminal and the drain terminal of the eighth transistor is directly connected to the other one of the source terminal and the drain terminal of the fourth transistor.

18. The semiconductor device according to claim 10 , wherein the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the seventh transistor the gate terminal of the third transistor, the gate terminal of the eighth transistor, and the one of the source terminal and the drain terminal of the fifth transistor are electrically isolated from each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 27, 2014
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 032540/0934 →
Priority Claims (1)
JP 2008-157400 · Jun 17, 2008 · national
Continuity (2)
Continuation 12477338 · Jun 3, 2009
Related Publication 20130069923A1 · Mar 21, 2013