Semiconductor device having angled trench walls
A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 μm or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×10 17 cm −3 or greater.
1. A semiconductor device comprising:
a substrate made of silicon carbide and provided with a trench that has a wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane and that has an opening at a side of one main surface thereof;
an oxide film formed on and in contact with said wall surface of said trench; and
an electrode disposed on and in contact with said oxide film,
said substrate including
a source region having first conductivity type and formed to include said one main surface and said wall surface,
a body region having second conductivity type and formed to include said wall surface and make contact with said source region, and
a drift region having the first conductivity type and formed to include said wall surface and make contact with said body region so as to sandwich said body region between said source region and said drift region,
said source region and said body region being formed by means of ion implantation,
said body region having a region that is sandwiched between said source region and said drift region and that has a thickness of 1 μm or smaller in a direction perpendicular to said one main surface,
said body region having an impurity concentration of 3×10 17 cm −3 or greater.
2. The semiconductor device according to claim 1 , wherein said body region has an impurity concentration of 2×10 18 cm −3 or smaller.
3. The semiconductor device according to claim 1 , wherein the region of said body region between said source region and said drift region has a thickness of 0.1 μm or greater in the direction perpendicular to said one main surface.
4. The semiconductor device according to claim 1 , wherein a distance from said one main surface to a contact surface between said body region and said drift region is 1.2 μm or smaller in the direction perpendicular to said one main surface.
5. The semiconductor device according to claim 1 , wherein said wall surface has an off orientation forming an angle of 5° or smaller relative to a <01-10> direction.
6. The semiconductor device according to claim 5 , wherein said wall surface has an off angle of not less than −3° and not more than 5° relative to a {03-38} plane in the <01-10> direction.
7. The semiconductor device according to claim 1 , wherein said wall surface has an off orientation forming an angle of 5° or smaller relative to a <−2110> direction.
8. The semiconductor device according to claim 1 , wherein said wall surface corresponds to a plane at a carbon plane side of silicon carbide constituting said substrate.