System and method for manufacturing contact
System and method for manufacturing contact. According to an embodiment, the present invention provides a method for manufacturing integrated circuits. The method includes a step for providing a semiconductor substrate. The method also includes a step for defining a plurality of contact regions on the semiconductor substrate. The method further includes a step for forming a plurality of dielectric structures on the plurality of contact regions. Additionally, the method includes a step for forming a plurality of openings on the semiconductor substrate. For example, each of the openings is characterized by at least a depth, a width, and an aspect ratio. Furthermore, the method includes a step for performing deposition within the openings using a first type of material, which includes a titanium material. The method additionally includes a step for performing annealing at a predetermined set of conditions.
1. A method for manufacturing integrated circuits comprising:
providing a semiconductor substrate;
defining a plurality of contact regions on the semiconductor substrate;
forming at least one dielectric structure on the plurality of contact regions;
forming a plurality of openings on the semiconductor substrate, each of the openings being characterized by at least a depth, a width, and an aspect ratio;
performing deposition within the openings using a titanium material;
forming, within the openings, an insulating material on the titanium material;
annealing the titanium material using a temperature range of 500 to 600 degrees Celsius and an oxygen concentration range of 141 to 1,000 parts per million, the annealing causing oxidation of the top surface of the titanium material to form a barrier configured to prevent silicon from diffusing through the titanium material; and
forming metal contacts by filling a tungsten material into the plurality of openings, the metal contacts being associated with a low resistance value.
2. The method of claim 1 further comprising forming a deposition layer using the titanium material.
3. The method of claim 2 wherein the deposition layer includes an etch back layer.
4. The method of claim 2 wherein the deposition layer includes an anti-reflection layer.
5. The method of claim 1 wherein annealing is performed for approximately thirty minutes.
6. The method of claim 1 wherein the integrated circuits comprise a DRAM cell.
7. The method of claim 1 wherein the insulating material comprises titanium nitride.
8. The method of claim 1 wherein the insulating material comprises titanium silicide.
9. The method of claim 1 wherein the performing deposition comprises forming an etch back layer.
10. The method of claim 1 wherein the performing deposition comprises forming an anti-reflection layer.
11. The method of claim 1 wherein the performing deposition comprises forming a glue layer.
12. The method of claim 1 wherein the metal contacts comprise a tungsten plug.
13. The method of claim 1 wherein the insulating material comprises a titanium nitride layer overlying the titanium material.
14. The method of claim 13 wherein the titanium material and the titanium nitride layer each have a thickness of about 250 Angstroms to about 300 Angstroms.
15. The method of claim 13 wherein the annealing causes oxidation of the titanium nitride layer configured to prevent diffusion of silicon into the tungsten material.
16. The method of claim 1 wherein the aspect ratio is characterized by a width-to-depth ratio of 1:10 or greater.
17. A method for manufacturing integrated circuits comprising:
providing a semiconductor substrate;
defining a plurality of contact regions on the semiconductor substrate;
forming at least one dielectric structure on the plurality of contact regions;
forming a plurality of openings on the semiconductor substrate, each of the openings being characterized by at least a depth, a width, and an aspect ratio;
performing deposition within the openings using a titanium material comprising a titanium layer and comprising a titanium nitride layer overlying the titanium layer;
annealing the titanium nitride layer to cause oxidization of the titanium nitride layer to form a barrier configured to prevent silicon from diffusing through the titanium nitride layer; and
forming metal contacts by filling a tungsten material into the plurality of openings, the metal contacts being associated with a low resistance value.
18. A method for manufacturing integrated circuits comprising:
providing a partially processed semiconductor substrate, the partially processed semiconductor substrate including at least one opening positioned within a dielectric structure;
forming a deposition layer within the at least one opening using a first type of material, the first type of material including a titanium material and including an insulating material;
annealing the titanium material using a temperature range of 500 to 600 degrees Celsius and an oxygen concentration range of 141 to 1,000 parts per million, the annealing causing oxidation of the top surface of the titanium material to form a barrier configured to prevent silicon from diffusing through the titanium material; and
forming metal contacts by filling a tungsten material into the plurality of openings, the metal contacts being associated with a low resistance value.
19. The method of claim 18 wherein the insulating material comprises titanium nitride.
20. The method of claim 18 wherein the deposition layer forms an ohmic contact with the dielectric structure.