Semiconductor package for high power devices
A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.
1. A semiconductor device package comprising:
a semiconductor die having a support can;
said support can comprising an insulation body with corresponding top and bottom conductive layers;
said top conductive layer having a depression therein defining a web surface;
said web surface having a plurality of dimples formed therein defining a desired location for said semiconductor die;
said semiconductor die being disposed in said desired location of said web surface.
2. The semiconductor device package of claim 1 , wherein said semiconductor die is a silicon MOSgated device.
3. The semiconductor device package of claim 1 , wherein said semiconductor die is an IGBT.
4. The semiconductor device package of claim 1 , further comprising an electrode on said semiconductor die, said electrode being mechanically and electrically fixed to said web surface.
5. The semiconductor device package of claim 4 , wherein said electrode is a drain electrode.
6. The semiconductor device package of claim 4 , wherein said electrode is a source electrode.
7. The semiconductor device package of claim 4 , wherein said electrode is a bump contact.
8. The semiconductor device package of claim 4 , wherein said electrode is a solderable pad.
9. The semiconductor device package of claim 1 , wherein said support can is a DBC wafer.
10. The semiconductor device package of claim 1 , wherein said insulation body is ceramic.
11. The semiconductor device package of claim 1 , wherein said top and bottom conductive layers comprise copper.
12. The semiconductor device package of claim 4 , wherein said electrode is soldered to a surface of said depression.
13. The semiconductor device package of claim 1 , further comprising a heat sink being electrically and mechanically fixed to said bottom conductive layer.
14. The semiconductor device package of claim 13 , further comprising fluid coolant channels in said heat sink.
15. The semiconductor device package of claim 1 , further comprising at least one via in said insulation body.
16. The semiconductor device package or claim 4 , further comprising an integrated circuit device having at least one terminal connected to said electrode.