IP Library › Granted Patent US 8,853,016
Granted Patent B2
US 8,853,016 · App. 13/758,869 · Granted Oct 7, 2014

Double gate thin-film transistor and OLED display apparatus including the same

Inventors: Hye-Hyang Park (Yongin-si, KR); Ki-Ju Im (Yongin-si, KR); Yong-Sung Park (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
H01L29/66969H01L51/0001H01L29/78648H01L29/7869H01L27/3262H01L27/1225
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Quick Facts
Patent No.
US 8,853,016
App. No.
13/758,869
Granted
Oct 7, 2014
Kind
B2
Abstract

A double gate thin-film transistor (TFT), and an organic light-emitting diode (OLED) display apparatus including the double gate TFT, includes a double gate thin-film transistor (TFT) including: a first gate electrode on a substrate; an active layer on the first gate electrode; source and drain electrodes on the active layer; a planarization layer on the substrate and the source and drain electrodes, and having an opening corresponding to the active layer; and a second gate electrode in the opening.

Claims (43)

1. A method of manufacturing an organic light-emitting diode (OLED) display apparatus, the method comprising:

forming a first gate electrode on a substrate;

forming a gate-insulating layer on the first gate electrode;

forming the active layer on the gate-insulating layer;

forming an interlayer insulating layer on the active layer;

forming source and drain electrodes on the interlayer insulating layer;

forming a planarization layer on the source and drain electrodes;

forming a pixel electrode on the planarization layer;

forming a pixel-defining layer (PDL) on the pixel electrode and the planarization layer;

forming a first opening for exposing a portion of the planarization layer corresponding to the first gate electrode by etching the PDL and the planarization layer, and a second opening for exposing a portion of the pixel electrode, by etching the PDL; and

forming an opposite electrode facing the pixel electrode in the first opening and facing the first gate electrode in the second opening.

2. The method of claim 1 , wherein the pixel electrode is electrically connected to one of the source or drain electrodes.

3. The method of claim 1 , wherein the opposite electrode is a second gate electrode corresponding to the first gate electrode.

4. The method of claim 1 , wherein a positive voltage is configured to be applied to the first gate electrode, and a negative voltage is configured to be applied to the opposite electrode.

5. The method of claim 1 , wherein the active layer comprises an oxide semiconductor.

6. The method of claim 1 , further comprising forming a light-emitting layer in the second opening before the forming of the opposite electrode.

7. A method of manufacturing a double gate thin-film transistor (TFT), the method comprising:

forming a first gate electrode on a substrate;

forming a gate-insulating layer on the first gate electrode;

forming an active layer on the gate-insulating layer;

forming an interlayer insulating layer on the active layer;

forming source and drain electrodes on the interlayer insulating layer;

forming a planarization layer on the source and drain electrodes;

forming an opening corresponding to the first gate electrode by etching the planarization layer; and

forming a second gate electrode in the opening, wherein the second gate electrode is a cathode electrode of an organic light-emitting diode (OLED) display apparatus.

8. The method of claim 7 , wherein the active layer comprises an oxide semiconductor.

9. The method of claim 7 , wherein a positive voltage is configured to be applied to the first gate electrode, and a negative voltage is configured to be applied to the second gate electrode.

10. A method of manufacturing an organic light-emitting diode (OLED) display apparatus, the method comprising:

forming a first gate electrode on a substrate;

forming an active layer on the first gate electrode;

forming source and drain electrodes on the active layer;

forming a planarization layer on the source and drain electrodes;

forming a pixel electrode on the planarization layer and electrically connected to one of the source or drain electrodes;

etching the planarization layer in a region corresponding to the first gate electrode;

forming a light-emitting layer on the pixel electrode; and

concurrently forming an opposite electrode corresponding to the pixel electrode and a second gate electrode corresponding to the first gate electrode by depositing a conductive material layer on an entire surface of the substrate including the light-emitting layer.

11. The method of claim 10 , further comprising:

forming a pixel-defining layer (PDL) on the pixel electrode and the planarization layer; and

forming a first opening for exposing a portion of the planarization layer corresponding to the first gate electrode by etching the PDL and the planarization layer, and a second opening for exposing a portion of the pixel electrode by etching the PDL;

wherein the conductive material layer is formed in the first and the second openings.

12. The method of claim 10 , further comprising:

forming a gate-insulating layer between the first gate electrode and the active layer; and

forming an interlayer insulating layer between the active layer and at least a portion of the source and drain electrodes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2016
From: MCDONALD, KEVIN G.; HOFFMAN, MARK
To: TILLAGE MANAGEMENT INCORPORATED
Reel/Frame 039064/0611 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2013
From: PARK, HYE-HYANG; IM, KI-JU; PARK, YONG-SUNG
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029814/0105 →
Priority Claims (1)
KR 10-2010-0065461 · Jul 7, 2010 · national
Continuity (2)
Division 13155329 · Jun 7, 2011
Related Publication 20130157399A1 · Jun 20, 2013