Contact for high-k metal gate device
An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure.
1. An integrated circuit, comprising:
a semiconductor substrate including a source region and a drain region;
a gate dielectric over the semiconductor substrate;
a metal gate structure over the semiconductor substrate and the gate dielectric and between the source and drain regions;
an interlayer dielectric (ILD) over the semiconductor substrate;
first and second contacts extending through the ILD and adjacent the source and drain regions, respectively; and
a third contact extending through the ILD and adjacent a top surface of the metal gate structure, the third contact further extending into an undercut region of the metal gate structure.
2. The integrated circuit of claim 1 , wherein the gate dielectric is a high-k dielectric.
3. The integrated circuit of claim 1 , wherein the metal gate structure includes copper.
4. The integrated circuit of claim 1 , wherein the third contact includes a glue layer including Ti and TiN.
5. The integrated circuit of claim 1 , wherein the three contacts comprise tungsten.
6. The integrated circuit of claim 5 further comprising:
a glue layer between the tungsten and the ILD.
7. The integrated circuit of claim 1 , wherein the undercut is of a type formed by an anisotropic etch.
8. An integrated circuit, comprising:
a substrate;
a metal structure over the substrate, the metal structure including an undercut;
a dielectric over the metal structure, the dielectric including a trench proximate to the undercut; and
a contact including a conductive material in the trench and in the undercut, the contact providing electrical connection to the metal structure.
9. The integrated circuit of claim 8 further comprising:
a high-k gate dielectric between the substrate and the metal structure.
10. The integrated circuit of claim 8 wherein the metal structure is a gate structure, and includes a plurality of metal layers including copper and titanium.
11. The integrated circuit of claim 8 wherein the undercut is contained within the metal structure.
12. The integrated circuit of claim 10 further comprising:
source and drain regions in the substrate and on opposite sides of the gate structure.
13. The integrated circuit of claim 8 further comprising:
a glue layer in the undercut.
14. A integrated circuit for making an integrated circuit, comprising:
a doped substrate with a high-k dielectric;
a metal gate structure over the high-k dielectric;
an interlayer dielectric (ILD) over the metal gate structure and the doped substrate;
a trench in the ILD to a top surface of the metal gate structure;
an undercut near the top surface of the metal gate structure; and
a conductive material filling the trench and the undercut.
15. The integrated circuit of claim 14 , wherein the metal gate structure includes at least one of copper or aluminum.
16. The integrated circuit of claim 9 further comprising:
a film between the metal gate structure and the ILD.
17. The integrated circuit of claim 16 wherein the film includes an oxynitride.