Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement
In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.
1. A method of forming a semiconductor structure, the method comprising:
depositing on a substrate a single-crystalline layer comprising a first III-nitride semiconductor material and a polycrystalline layer comprising a second III-nitride semiconductor material, thereby forming a semiconductor article; and
after the deposition of the single-crystalline layer and the polycrystalline layer, cooling the semiconductor article from a growth temperature to approximately room temperature, thereby forming a second semiconductor article, the second semiconductor article (a) being substantially crack-free and (b) having (i) a first surface comprising the single-crystalline first III-nitride semiconductor material and (ii) a second surface, opposite the first surface, comprising the polycrystalline second III-nitride semiconductor material.
2. The method of claim 1 , further comprising planarizing the first surface of the second semiconductor article.
3. The method of claim 2 , wherein the first surface of the second semiconductor article is planarized via chemical-mechanical polishing.
4. The method of claim 1 , wherein, during cooling from the growth temperature to approximately room temperature, the second semiconductor article separates from a portion of the semiconductor article.
5. The method of claim 1 , wherein the substrate comprises sapphire.
6. The method of claim 1 , wherein the first III-nitride semiconductor material comprises a material selected from the group consisting of GaN, AlN, InN, and ternary and quaternary alloys and mixtures including one or more thereof.
7. The method of claim 6 , wherein the first III-nitride semiconductor material comprises GaN.
8. The method of claim 1 , wherein the second III-nitride semiconductor material comprises a material selected from the group consisting of GaN, AlN, InN, and ternary and quaternary alloys and mixtures including one or more thereof.
9. The method of claim 8 , wherein the second III-nitride semiconductor material comprises GaN.
10. The method of claim 9 , wherein the first III-nitride semiconductor material comprises GaN.
11. The method of claim 1 , wherein the substrate is selected from the group consisting of silicon carbide, gallium arsenide, zinc oxide, silicon, spinel, lithium gallate, and lithium aluminate.
12. The method of claim 1 , wherein the semiconductor article comprises an epitaxial nitride layer between the substrate and the single-crystalline layer comprising the first III-nitride semiconductor material.
13. The method of claim 12 , wherein the epitaxial nitride layer comprises AlN.
14. The method of claim 1 , wherein the single-crystalline layer comprising the first III-nitride semiconductor material is deposited via hydride vapor phase epitaxy.
15. The method of claim 1 , wherein the polycrystalline layer comprising the second III-nitride semiconductor material is deposited via hydride vapor phase epitaxy.
16. The method of claim 1 , wherein depositing the single-crystalline layer comprising the first III-nitride semiconductor material comprises doping with at least one of an n-type dopant, a p-type dopant, or a deep-level acceptor.