IP Library Granted Patent US 8,916,451
Granted Patent B2
US 8,916,451 · App. 13/759,724 · Granted Dec 23, 2014

Thin film wafer transfer and structure for electronic devices

Inventors: Can Bayram (Ossining, NY); Jack O. Chu (Manhasset Hills, NY); Christos Dimitrakopoulos (Baldwin Place, NY); Jeehwan Kim (White Plains, NY); Hongsik Park (Yorktown Heights, NY); Devendra K. Sadana (Pleasantville, NY)
Assignee: International Business Machines Corporation
H01L21/76251
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Quick Facts
Patent No.
US 8,916,451
App. No.
13/759,724
Granted
Dec 23, 2014
Kind
B2
Abstract

A method for wafer transfer includes forming a spreading layer, including graphene, on a single crystalline SiC substrate. A semiconductor layer including one or more layers is formed on and is lattice matched to the crystalline SiC layer. The semiconductor layer is transferred to a handle substrate, and the spreading layer is split to remove the single crystalline SiC substrate.

Claims (36)

1. A method for wafer transfer, comprising:

forming a spreading layer on a single crystalline substrate, the spreading layer including a material having strong bonds in two dimensions and weak bonds in a third dimension, the spreading layer being spread to lattice match the single crystalline substrate;

growing a crystalline layer on the spreading layer such that the crystalline layer is lattice matched to the single crystalline substrate;

forming one or more semiconductor layers on the crystalline layer, wherein the crystalline layer includes SiC, the spreading layer includes grapheme and the one or more semiconductor layers includes GaN;

transferring the one or more semiconductor layers to a handle substrate; and

splitting the spreading layer along the weak bonds to remove the single crystalline substrate.

2. The method as recited in claim 1 , wherein the spreading layer includes one to five monolayers of graphene.

3. The method as recited in claim 1 , wherein the single crystalline substrate includes one of SiC, SiGe, a III-nitride, III-arsenide, and a III-phosphide.

4. The method as recited in claim 1 , wherein growing the crystalline layer on the spreading layer includes epitaxially growing the crystalline layer.

5. The method as recited in claim 1 , wherein the single crystalline substrate includes SiC and forming a spreading layer includes thermally decomposing the SiC to form a graphene spreading layer.

6. The method as recited in claim 1 , wherein forming the spreading layer includes epitaxially growing a graphene spreading layer.

7. The method as recited in claim 1 , wherein the one or more III-nitride layers form active layers for an electronic device.

8. The method as recited in claim 1 , further comprising reusing the single crystalline substrate for further processing.

9. A method for wafer transfer to form an electronic device, comprising:

forming a spreading layer on a single crystalline substrate;

growing a crystalline layer on the spreading layer to form a first contact layer such that the crystalline layer is lattice matched to the single crystalline substrate;

forming an active layer including one or more III-nitride layers on the crystalline layer, wherein the crystalline layer includes SiC, the spreading layer includes graphene and the one or more III-nitride layers includes GaN;

forming a second contact layer over the active layer, wherein the active layer is disposed vertically between the first and second contact layers;

transferring the second contact layer to a handle substrate; and

splitting the spreading layer to remove the single crystalline substrate.

10. The method as recited in claim 9 , wherein the spreading layer includes one to five monolayers of graphene.

11. The method as recited in claim 9 , wherein forming the active layer includes forming a multiple quantum well (MQW) structure.

12. The method as recited in claim 11 , wherein MQW structure includes a plurality of GaN/InGaN periods having a total thickness of less than about 100 nm.

13. The method as recited in claim 9 , further comprising reusing the single crystalline substrate for further processing.

14. The method as recited in claim 9 , wherein the first contact layer and the second contact layer are separated by a distance of 100 nm or less.

15. The method as recited in claim 9 , wherein the single crystalline substrate includes one of SiC, SiGe, a III-nitride, III-arsenide, and a III-phosphide.

16. The method as recited in claim 9 , wherein the single crystalline substrate includes SiC and forming a spreading layer includes thermally decomposing the SiC to form a graphene spreading layer.

17. The method as recited in claim 9 , wherein forming the spreading layer includes epitaxially growing a graphene spreading layer.

18. A method for wafer transfer, comprising:

forming a spreading layer, including graphene, on a single crystalline SiC substrate;

growing a crystalline SiC layer on the spreading layer;

forming a semiconductor layer including one or more layers lattice matched to the single crystalline SiC substrate;

transferring the semiconductor layer to a handle substrate; and

splitting the spreading layer to remove the single crystalline SiC substrate.

19. The method as recited in claim 18 , further comprising reusing the single crystalline SiC for further processing.

20. The method as recited in claim 18 , wherein the single crystalline substrate includes SiC and forming a spreading layer includes one of: thermally decomposing the SiC to form a graphene spreading layer; and epitaxially growing a graphene spreading layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2013
From: BAYRAM, CAN; CHU, JACK O.; DIMITRAKOPOULOS, CHRISTOS; KIM, JEEHWAN; PARK, HONGSIK; SADANA, DEVENDRA K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 029757/0829 →
Continuity (1)
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