SiC epitaxial wafer and semiconductor device
An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.
1. An SiC epitaxial wafer comprising:
an SiC substrate; and
a p-type first SiC epitaxial layer formed on the SiC substrate, the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A and the n-type impurity being an element D, the element A and the element D forming at least a first combination or a second combination, the first combination being a combination of the element A selected from a group consisting of Al (aluminum), Ga (gallium), and In (indium) and the element D being N (nitrogen), the second combination being a combination of the element A being B (boron) and the element D being P (phosphorus), a ratio of a concentration of the element D to a concentration of the element A forming at least one of the combinations being higher than 0.33 but lower than 1.0.
2. The wafer according to claim 1 , further comprising:
an n-type second SiC epitaxial layer formed between the SiC substrate and the first SiC epitaxial layer; and
a p-type third SiC epitaxial layer formed between the second SiC epitaxial layer and the first SiC epitaxial layer, the third SiC epitaxial layer having a lower p-type impurity concentration than the first SiC epitaxial layer,
wherein
the SiC substrate is an n-type SiC substrate and has a higher n-type impurity concentration than the second SiC epitaxial layer, and
the concentration of the element A is not lower than 1×10 18 cm −3 and not higher than 1×10 22 cm −3 .
3. The wafer according to claim 1 , wherein the ratio of the concentration of the element D to the concentration of the element A is higher than 0.40 but lower than 0.95.
4. The wafer according to claim 1 , wherein an acceptor level of the element A is 150 meV or lower.
5. The wafer according to claim 1 , wherein 90% or more of the element D is in a lattice site location nearest to the element A.
6. An SiC epitaxial wafer comprising:
an SiC substrate; and
an n-type first SiC epitaxial layer formed on the SiC substrate, the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A and the n-type impurity being an element D, the element A and the element D forming at least a first combination or a second combination, the first combination being a combination of the element A selected from a group consisting of Al (aluminum), Ga (gallium), and In (indium) and the element D being N (nitrogen), the second combination being a combination of the element A being B (boron) and the element D being P (phosphorus), a ratio of a concentration of the element A to a concentration of the element D forming at least one of the combinations being higher than 0.40 but lower than 0.95.
7. The wafer according to claim 6 , further comprising
an n-type second SiC epitaxial layer formed between the SiC substrate and the first SiC epitaxial layer, the second SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A and the n-type impurity being an element D, the element A and the element D forming at least a first combination or a second combination, the first combination being a combination of the element A selected from a group consisting of Al (aluminum), Ga (gallium), and In (indium) and the element D being N (nitrogen), the second combination being a combination of the element A being B (boron) and the element D being P (phosphorus), a ratio of a concentration of the element A to a concentration of the element D forming at least one of the combinations being higher than 0.40 but lower than 0.95,
wherein
the SiC substrate is an n-type SiC substrate, and the concentration of the n-type impurity in the second SiC epitaxial layer is lower than an n-type impurity concentration in the SiC substrate and is higher than the concentration of the n-type impurity in the first SiC epitaxial layer, and
the concentration of the element D in the first SiC epitaxial layer is not lower than 1×10 15 cm −3 and not higher than 5×10 16 cm −3 .
8. The wafer according to claim 6 , wherein the ratio of the concentration of the element A to the concentration of the element D is not lower than 0.45 and not higher than 0.75.
9. The wafer according to claim 6 , wherein a donor level of the element D is 40 meV or lower.
10. The wafer according to claim 6 , wherein 90% or more of the element A is in a lattice site location nearest to the element D.
11. A semiconductor device comprising:
an n-type first SiC epitaxial layer;
a p-type second SiC epitaxial layer formed on the first SiC epitaxial layer, the second SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A and the n-type impurity being an element D, the element A and the element D forming at least a first combination or a second combination, the first combination being a combination of the element A selected from a group consisting of Al (aluminum), Ga (gallium), and In (indium) and the element D being N (nitrogen), the second combination being a combination of the element A being B (boron) and the element D being P (phosphorus), a ratio of a concentration of the element D to a concentration of the element A in the at least one of the combinations being higher than 0.33 but lower than 1.0, the concentration of the element A forming at least one of the combinations being not lower than 1×10 18 cm −3 and not higher than 1×10 22 cm −3 ;
a first electrode formed on the second SiC epitaxial layer;
a second electrode formed on the opposite side of the first SiC epitaxial layer from the first electrode; and
a groove portion formed on both sides of the first electrode, the groove portion extending from a surface of the second SiC epitaxial layer to the first SiC epitaxial layer.
12. The device according to claim 11 , further comprising
a p-type third SiC epitaxial layer formed between the first SiC epitaxial layer and the second SiC epitaxial layer, the third SiC epitaxial layer having a lower p-type impurity concentration than the second SiC epitaxial layer.
13. The device according to claim 11 , wherein the ratio of the concentration of the element D to the concentration of the element A is higher than 0.40 but lower than 0.95.
14. The device according to claim 11 , wherein an acceptor level of the element A is 150 meV or lower.
15. The device according to claim 11 , wherein 90% or more of the element D is in a lattice site location nearest to the element A.
16. A semiconductor device comprising:
an n-type first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A and the n-type impurity being an element D, the element A and the element D forming at least a first combination or a second combination, the first combination being a combination of the element A selected from a group consisting of Al (aluminum), Ga (gallium), and In (indium) and the element D being N (nitrogen), the second combination being a combination of the element A being B (boron) and the element D being P (phosphorus), a ratio of a concentration of the element A to a concentration of the element D forming at least one of the combinations being higher than 0.40 but lower than 0.95;
a p-type first SiC region formed in a surface of the first SiC epitaxial layer;
an n-type second SiC region formed in a surface of the first SiC region;
a gate insulating film formed continuously on the surfaces of the first SiC epitaxial layer and the first SiC region;
a gate electrode formed on the gate insulating film;
a first electrode formed on the second SiC region; and
a second electrode formed on the opposite side of the first SiC epitaxial layer from the first electrode.
17. The device according to claim 16 , wherein the concentration of the element D in the first SiC epitaxial layer is not lower than 1×10 15 cm −3 and not higher than 5×10 16 cm −3 .
18. The device according to claim 16 , wherein the ratio of the concentration of the element A to the concentration of the element D is not lower than 0.45 and not higher than 0.75.
19. The device according to claim 16 , wherein a donor level of the element D is 40 meV or lower.
20. The device according to claim 16 , wherein 90% or more of the element A is in a lattice site location nearest to the element D.