Single layer coreless substrate
View Patent ↗An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.
1. A method of fabricating an electronic chip package comprising the steps of:
(a) selecting a sacrificial substrate;
(b) depositing an etchant resistant barrier layer onto said sacrificial substrate;
(c) plating a layer of via posts;
(d) laminating the layer of via posts with a dielectric material;
(e) thinning and planarizing the dielectric layer;
(f) plating a layer of routing features over the via layer;
(g) attaching at least one chip, and
(h) encapsulating the at least one chip and routing features with a second dielectric material;
(i) removing the sacrificial substrate, and
(j) removing barrier layer.
2. The method of claim 1 wherein step (g) comprises wire bonding the at least one chip to the routing features and step (h) comprises encapsulating with a molding material.
3. The method of claim 1 wherein step (g) comprises flip chip bonding the at least one chip to the routing features with an array of bumps.
4. The method of claim 3 , wherein step (h) comprises encapsulating with a glass fiber in polymer pre-preg.
5. The method of claim 1 , wherein the sacrificial substrate comprises a peelable copper substrate, a release layer and an ultra-fine copper foil, and step (i) of removal of the sacrificial substrate comprises peeling away the peelable copper substrate and etching away the remaining copper foil.
6. The method of claim 1 further comprising the step (k) of terminating the substrate by removing the etchant resistant barrier layer to expose ends of vias on outer surfaces of the stack and applying terminations to said ends of vias.
7. The method of claim 1 , wherein the barrier layer of step (b) is deposited to a thickness in the range of 0.1 micron to tens of microns and either:
comprises a metal selected from the list of tantalum, tungsten, titanium, titanium-tantalum alloy, titanium-tungsten alloy, nickel, tin, lead, and tin-lead alloy and said depositing comprises sputtering,
or comprises a metal selected from the list of nickel, tin, lead, and tin-lead alloy and said depositing is by a process selected from the list of electroplating and electro-less plating.
8. The method of claim 7 wherein step (c) of plating a layer of via posts comprises pattern plating said layer of via posts by the sub-steps of:
laying down a layer of photo-resist;
developing a pattern of vias in said layer of photo-resist;
plating copper into said pattern, and
stripping away the photo-resist leaving said vias upstanding.
9. The method of claim 7 , wherein step (c) of plating a layer of via posts comprises depositing a termination material and building via posts by onto said termination material.
10. The method of claim 9 , wherein said termination metal comprises at least of the group consisting of tin, tin-lead alloy, gold, silver and palladium.
11. The method of claim 1 , wherein step (c) of plating a layer of via posts comprises panel plating said layer of via posts by the sub-steps of:
panel plating a continuous layer of copper;
depositing a layer of photo-resist over said continuous layer of copper;
developing a pattern of vias in said layer of photo-resist;
etching away surplus copper to leave said pattern, and
stripping away the developed photo-resist leaving said vias upstanding.