IP Library Granted Patent US 8,956,919
Granted Patent B2
US 8,956,919 · App. 13/142,172 · Granted Feb 17, 2015

Structure for multi-row leadframe and semiconductor package thereof and manufacture method thereof

Inventors: Hyun A. Chun (Gyeonggi-do, KR); Jae Bong Choi (Gyeonggi-do, KR); Sung Won Lee (Seoul, KR); Sung Wuk Ryu (Seoul, KR); Hyuk Soo Lee (Gyeonggi-do, KR); Sai Ran Eom (Incheon, KR)
Assignee: LG Innotek Co., Ltd.
H01L21/4832H01L23/49582H01L24/29H01L2224/48091H01L2224/48247H01L2224/73265H01L2224/92247H01L2924/01046H01L2924/01078H01L2924/01079H01L24/48H01L2224/32245H01L2924/01067H01L2924/01322H01L2924/0132H01L2924/01029
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Quick Facts
Patent No.
US 8,956,919
App. No.
13/142,172
Granted
Feb 17, 2015
Kind
B2
Abstract

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Claims (46)

1. A manufacturing method of multi-row leadframe, comprising:

forming a plating pattern on a leadframe material (first step);

forming a protective pattern on the plating pattern (second step); and

forming a pattern by using the protective pattern as a mask (third step);

wherein a width (T 1 ) of an upper protective pattern formed on an upper surface of the leadframe material is wider than a width (T 2 ) of the plating pattern; and

wherein the first step of forming a plating pattern on the leadframe material includes: coating photosensitive material on double sides or a single side of the leadframe material, exposing and developing to form a leadframe pattern (a step); and carrying out a plating on the leadframe pattern (b step).

2. The method of claim 1 , wherein the material applied to the process of forming the plating pattern in the first step uses a single alloy from one of Ni, Pd, Au, Sn, Ag, Co, and Cu, or a binary alloy or ternary alloy, and is in a single layer or a double layer.

3. The method of claim 1 , wherein the first step further comprises a (c) step of exfoliating the photosensitive material after forming the plating pattern.

4. A manufacturing method of multi-row leadframe, comprising:

forming a plating pattern on a leadframe material (first step);

forming a protective pattern on the plating pattern (second step);and

forming a pattern by using the protective pattern as a mask (third step);

wherein a width (T 1 ) of an upper protective pattern formed on an upper surface of the leadframe material is wider than a width (T 2 ) of the plating pattern, and

wherein the second step includes using a photolithography method by coating the photosensitive material on double sides or a single side of the leadframe material formed with the plating pattern.

5. The method of claim 4 , wherein the second step includes:

coating the photosensitive material on double sides of the leadframe material,

wherein an exposure and development of pattern are carried out on the upper surface of the leadframe material to form an upper protective pattern, and

an overal exposure is carried out on the lower surface of the leadframe material to form a lower protective pattern.

6. A manufacturing method of multi-row leadframe, comprising:

forming a plating pattern on a leadframe material (first step);

forming a protective pattern on the plating pattern (second step); and

forming a pattern by using the protective pattern as a mask (third step);

wherein a width (T 1 ) of an upper protective pattern formed on an upper surface of the leadframe material is wider than a width (T 2 ) of the plating pattern,

wherein the protective pattern is formed in a structure encompassing an upper portion and a lateral portion of the plating pattern,

wherein the third step includes etching an exposed upper surface of the leadframe excluding an upper protective pattern portion, and

wherein a step of exfoliating the protective pattern is further included subsequent to the third step.

7. A manufacturing method of semiconductor package using multi-row leadframe, the method comprising:

forming a plating pattern on a leadframe material (first step);

forming a protective pattern on the plating pattern (second step);

forming a pattern using the protective pattern as a mask (third step); and

exfoliating the protective pattern, and carrying out semiconductor chip mounting, wire bonding and epoxy molding, and completing the semiconductor package through back etching (fourth step),

wherein the second step is characterized in that a width (T 1 ) of an upper protective pattern formed on an upper surface of the leadframe material is wider than a width (T 2 ) of the plating pattern.

8. The method of claim 7 , wherein the first step of forming a plating pattern on the leadframe material includes: coating photosensitive material on double sides or a single side of the leadframe material, exposing and developing to form a leadframe pattern (a step); and carrying out a plating on the leadframe pattern (b step).

9. The method of claim 7 , wherein the second step includes using a photolithography method by coating the photosensitive material on double sides or a single side of the leadframe material formed with the plating pattern.

10. A structure for multi-row leadframe in the leadframe manufacturing method, comprising:

forming at least one or more patterns on an upper surface or a lower surface of the leadframe;

and

forming the leadframe including a plating pattern on one or more portions not formed with the pattern, wherein a width (T 3 ) of the upper pattern surface of the leadframe is wider than the width (T 2 ) of the plating pattern; and

wherein a periphery of a leadframe strip is formed with an exposed structure.

11. A semiconductor package, comprising:

forming at least one or more patterns on an upper surface or a lower surface of a leadframe material; and

forming a leadframe including a plating pattern on one or more portions not formed with the pattern, wherein the semiconductor package is characterized by:

a multi-row leadframe having a width (T 3 ) of the upper pattern surface of the leadframe that is wider than a width (T 2 ) of the plating pattern;

a semiconductor chip;

a wire bonding; and

an epoxy molding.

Assignments (3)
CHANGE OF NAME Recorded May 14, 2025
From: ALS CO., LTD.
To: INNOTRO CO., LTD.
Reel/Frame 071275/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: LG INNOTEK CO., LTD.
To: ALS CO., LTD.
Reel/Frame 035598/0488 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2011
From: CHUN, HYUNA; CHOI, JAEBONG; LEE, SUNGWON; RYU, SUNGWUK; LEE, HYUKSOO; EOM, SAIRAN
To: LG INNOTEK CO., LTD.
Reel/Frame 027109/0161 →
Priority Claims (1)
KR 10-2008-0132887 · Dec 24, 2008 · national
Continuity (1)
Related Publication 20120038036A1 · Feb 16, 2012