Method for manufacturing semiconductor thick metal structure
A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N 2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.
1. A method of manufacturing of a semiconductor thick metal structure, comprising:
a thick metal deposition step comprising: depositing a barrier layer, a metal layer, and an anti-reflection layer on a surface of a semiconductor chip, wherein the metal layer has a thickness of 3.5 μm to 4.5 μm; the anti-reflection layer comprises a titanium layer and a titanium nitride layer;
a metal patterning step comprising: coating a photoresist layer on the anti-reflection layer;
exposing the photoresist layer using a mask, such that partial photoresist corresponding to patterns of the mask becomes soluble; etching and removing the soluble photoresist;
etching the metal layer using a four-step etching method with the remaining photoresist as a mask to form a surface pattern having a concavo-convex structure with a feature size of 1.5 μm to 2 μm; and
a passivation step comprising: forming a passivation layer on a surface of the metal layer having the concavo-convex structure, wherein the passivation layer is half-full filled in the concavo-convex structure of the metal layer.
2. The method according to claim 1 , wherein the thick metal deposition step comprises:
forming the barrier layer on the surface of the chip, wherein the barrier layer comprises a titanium layer and a titanium nitride layer, the titanium layer has a thickness of 300 Å to 600 Å, the titanium nitride layer has a thickness of 300 Å to 800 Å;
forming the metal layer on the barrier layer, wherein the metal layer comprises an aluminum-copper layer and an Al—Si—Cu layer; and
forming the anti-reflection layer on the metal layer, wherein the anti-reflection layer comprises the titanium layer and the titanium nitride layer, the titanium layer has a thickness of 100 Å to 400 Å, and the titanium nitride layer has a thickness of 250 Å to 400 Å.
3. The method according to claim 2 , wherein the barrier layer is formed using a physical vapor deposition process with the following parameters: a temperature is 300° C. to 400° C.; a power of forming the titanium layer is 2500 W to 4000 W; an Ar flow is 30 SCCM to 80 SCCM, the time is controlled to be 15 s to 30 s; a power of forming the titanium nitride layer is 7000 W to 10000 W; an Ar flow is 20 SCCM to 45 SCCM; a N 2 flow is 80 SCCM to 135 SCCM; a time is 15 s to 25 s.
4. The method according to claim 2 , wherein the metal layer is formed using a physical vapor deposition process with the following parameters: a deposition temperature is 300° C. to 400° C.; a power is 8000 W to 14000 W; an Ar flow is 30 SCCM to 80 SCCM; a time is 150 s to 300 s.
5. The method according to claim 2 , wherein the anti-reflection layer is formed using a physical vapor deposition process with the following parameters: a temperature is 300° C. to 400° C.; a power of forming the titanium layer is 2500 W to 4000 W; an Ar flow is 30 SCCM to 80 SCCM, the time is controlled to be 10 s to 20 s; a power of forming the titanium nitride layer is 7000 W to 10000 W; an Ar flow is 20 SCCM to 45 SCCM; a N 2 flow is 80 SCCM to 135 SCCM; a time is 10 s to 15 s.
6. The method according to claim 1 , wherein the four-step etching method comprises:
performing physical bombardment to the surface using Ar to remove residual photoresist on a surface of the metal region to be etched;
a main etching step comprising: etching the metal layer using boron trichloride gas and chlorine by an automatically-grabbing-end method, wherein an etching rate of the metal layer and an etching rate of the photoresist are determined by a ratio of the boron trichloride gas to the chlorine, such that a final effective residual thickness of the photoresist is greater than 4000 Å, and a protection of a sidewall of the concavo-convex structure of the metal layer is enhanced by nitrogen;
a main over-etching step comprising: performing an over-etching step with the same parameters as the main etching step, wherein a time for over-etching is 20 s to 50 s; and
a subsidiary over-etching step, wherein a time of the subsidiary over-etching step is less than 100 s, and a ratio of the chlorine to the boron trichloride gas is 1 to 1.5.
7. The method according to claim 6 , wherein parameters of the physical bombardment step using Ar comprises: an Ar flow is 40 SCCM to 80 SCCM, a pressure is 8 mT to 15 mT, a time is 20 s to 40 s; a power is 600 W to 1000 W.
8. The method according to claim 6 , wherein parameters of the main etching step comprises: a temperature is 40° C. to 70° C., a boron trichloride flow is 50 SCCM to 80 SCCM, a chlorine gas flow is 80 SCCM to 120 SCCM, a nitrogen flow is 5 SCCM to 30 SCCM, a pressure is 10 mT to 16 mT, a power is 600 W to 1000 W.
9. The method according to claim 6 , wherein the passivation step comprises:
depositing a silicon-rich oxide layer having a thickness of 50 nm to 200 nm on a surface of the metal layer having the concavo-convex structure;
depositing a high density plasma silicon dioxide layer having a thickness of 1000 nm to 1500 nm on a surface of the silicon-rich oxide layer using a high-density plasma deposition process; and
depositing a silicon nitride layer having a thickness of 500 nm to 800 nm on the high density plasma silicon dioxide layer.
10. The method according to claim 9 , wherein parameters of the step of depositing the silicon-rich oxide layer comprises: a temperature is 350° C. to 450° C., a N 2 O flow is 200 SCCM to 350 SCCM, a SiH 4 flow is 70 SCCM to 120 SCCM, a power is 150 W to 250 W, a time is 5 s to 20 s.
11. The method according to claim 9 , wherein parameters of the step of depositing the high density plasma silicon dioxide layer comprises: a temperature is 350° C. to 450° C., a SiH 4 flow is 50 SCCM to 150 SCCM, an O 2 flow is 50 SCCM to 200 SCCM, an Ar flow is 300 SCCM to 450 SCCM, a power is 2000 W to 4000 W, a time is 100 s to 200 s.
12. The method according to claim 9 , wherein parameters of the step of depositing the silicon nitride layer comprises: a temperature is 350° C. to 450° C., a SiH 4 flow is 500 SCCM to 800 SCCM, an N 2 flow is 7000 SCCM to 9000 SCCM, an NH 3 flow is 250 SCCM to 400 SCCM, a power is 500 W to 900 W, a time is 40 s to 60 s.
13. The method according to claim 1 , wherein during the step of thick metal deposition, the depositions of the barrier layer, the metal layer, and the anti-reflection layer are performed in one machine.
14. The method according to claim 1 , wherein the photoresist layer has a thickness of 3 μm to 3.5 μm.
15. The method according to claim 1 , wherein after the passivation step, a bonding pad window is fabricated by a photolithography/etching process.