Switched resonant ultrasonic power amplifier system
A switched resonant power amplifier system for ultrasonic transducers is disclosed. The system includes an amplifier that receives and processes a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device. An output control circuit receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal, and generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal. A compensated drive circuit receives and processes the compensated clock signal for generating the divider reference signal, and for generating the driver output signal.
1. A system for controlling an output of a surgical device, the system comprising:
a driver configured to provide a pair of driver output signals approximately 180° out of phase with respect to each other;
an amplifier including a pair of switching elements configured to receive and process the pair of driver output signals and produce a respective amplified driver output signal that drives the surgical device and controls the output thereof; and
a wave shaping circuit configured to receive a feedback signal from the surgical instrument and provide a square wave output having a frequency that is substantially identical to a frequency of the feedback signal, the wave shaping circuit configured to provide a reset signal having a substantial identical frequency and 180° out of phase with respect to the square wave.
2. The system of claim 1 , wherein the reset signal is communicated to a compensating circuit for controlling the generation of a compensated reference signal.
3. The system of claim 2 , wherein the compensated reference signal is compared to a divider reference signal for producing error signal, wherein the divider reference signal is representative of a compensated clock signal.
4. The system of claim 3 , wherein, when a phase difference between the compensated reference signal and the divider signal is at a minimum value, the phase error signal will have a first value.
5. The system of claim 3 , wherein, when a phase difference between the compensated reference signal and the divider signal is at a maximum value, the phase error signal will have a second value.
6. The system of claim 3 , further including a delay circuit that is configured to control the timing of the compensated clock signal.
7. The system of claim 3 , wherein the compensated clock signal is coupled to an input of an input of divider where a frequency of compensated clock signal is stepped-down by the divider to a desired counter output signal.
8. The system of claim 7 , wherein the divider is coupled to a flip-flop for splitting the counter output signal into complementary square waves.
9. The system of claim 8 , wherein each square wave is substantially 180° out-of-phase with respect to each other.
10. The system of claim 9 , wherein each square wave has a frequency that is substantially one-half of the frequency of the counter output signal.