IP Library Granted Patent US 8,981,384
Granted Patent B2
US 8,981,384 · App. 13/805,279 · Granted Mar 17, 2015

Semiconductor device and method for manufacturing same

Inventor: Takeyoshi Masuda (Osaka-shi, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L29/1608H01L29/8613H01L29/0623H01L21/3065H01L29/7397H01L29/045H01L29/4236H01L29/66068H01L29/7813H01L21/0445Y10S438/931
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Quick Facts
Patent No.
US 8,981,384
App. No.
13/805,279
Granted
Mar 17, 2015
Kind
B2
Abstract

There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Claims (24)

1. A semiconductor device, comprising:

a substrate having a main surface; and

a silicon carbide layer formed on said main surface of said substrate,

said silicon carbide layer including a voltage holding layer and a trench having a bottom portion in said voltage holding layer, said trench further having an end surface inclined relative to said main surface,

an electric field relaxing region being formed at said bottom portion of said trench in said voltage holding layer, said electric field relaxing region having a different conductivity type from that of said voltage holding layer,

a gate electrode being formed inside said trench, a single-layered gate insulating film is formed between said gate electrode and said end surface of said trench, and

said end surface substantially including one of a {03-3-8} plane and a {01-1-4} plane in a case where said silicon carbide layer is of hexagonal crystal type, and substantially including a {100} plane in a case where said silicon carbide layer is of cubic crystal type.

2. The semiconductor device according to claim 1 , wherein said end surface includes an active region.

3. The semiconductor device according to claim 2 , wherein said active region includes a channel region.

4. The semiconductor device according to claim 1 , wherein

said silicon carbide layer includes a mesa structure having a side surface constituted by said end surface, at its main surface located opposite to its surface facing said substrate, and

a PN junction is formed in said mesa structure.

5. The semiconductor device according to claim 1 , wherein at least a portion of said end surface constitutes a termination structure.

6. A method for manufacturing a semiconductor device, comprising the steps of:

preparing a substrate on which a silicon carbide layer including a voltage holding layer is formed;

forming a trench having a bottom portion in said voltage holding layer, said trench further having a side wall substantially perpendicular to said main surface;

forming an end surface inclined relative to a main surface of said silicon carbide layer by removing a portion of said side wall of said trench by etching by heating said silicon carbide layer while exposing said silicon carbide layer to a reaction gas containing oxygen and chlorine;

forming an electric field relaxing region at said bottom portion of said trench in said voltage holding layer, said electric field relaxing region having a different conductivity type from that of said voltage holding layer; and

forming a structure included in the semiconductor device, using said end surface,

said end surface substantially including one of a {03-3-8} plane and a {01-1-4} plane in a case where said silicon carbide layer is of hexagonal crystal type, and substantially including a {100} plane in a case where said silicon carbide layer is of cubic crystal type.

7. The method for manufacturing the semiconductor device according to claim 6 , further comprising the step of forming a mask layer having a pattern on said main surface of said silicon carbide layer before the step of forming said end surface,

wherein, in the step of forming said end surface, etching for forming a trench is performed using said mask layer as a mask.

8. The method for manufacturing the semiconductor device according to claim 6 , wherein, in the reaction gas used in the step of forming said end surface, a ratio of a flow rate of oxygen to a flow rate of chlorine is not less than 0.1 and not more than 2.0.

9. The method for manufacturing the semiconductor device according to claim 6 , wherein, in the step of forming said end surface, said silicon carbide layer is heated at a temperature of not less than 700° C. and not more than 1200° C.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2012
From: MASUDA, TAKEYOSHI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 029494/0060 →
Priority Claims (1)
JP 2010-174664 · Aug 3, 2010 · national
Continuity (1)
Related Publication 20130112996A1 · May 9, 2013