IP Library › Granted Patent US 9,002,694
Granted Patent B2
US 9,002,694 · App. 13/463,034 · Granted Apr 7, 2015

Verification of design derived from power intent

Inventors: Xiushan Feng (Austin, TX); Jayanta Bhadra (Austin, TX); Scott R. Little (Hillsboro, OR)
Assignee: Freescale Semiconductors, Inc.
G06F17/5036G06F17/5022G06F1/3203G06F2217/78
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Quick Facts
Patent No.
US 9,002,694
App. No.
13/463,034
Granted
Apr 7, 2015
Kind
B2
Abstract

An approach is provided in which a power design verification system retrieves a power intent data corresponding to a power design, which identifies the power design's power modes and power mode transition conditions. The power design verification system selects one of the power mode transition conditions, which identifies input signals that invoke a transition from a first power mode to a second power mode. In turn, the power design verification system generates simulation stimuli based upon the identified input signals and simulates the power design utilizing the generated simulation stimuli accordingly.

Claims (64)

1. A method comprising:

generating a power state graph based upon power intent data of a power design, wherein the power state graph comprises a plurality of edges based upon a plurality of power mode transition conditions included in the power intent data to transition between one or more of a plurality of power modes of the power design;

updating the power intent data to include one or more new power mode transition conditions in response to determining that a transition sequence comprising one or more of the plurality of edges fails to exist in the power state graph from a selected first power mode to a selected second power mode, the selected first power mode and the selected second power mode included in the plurality of power modes;

generating an updated power state graph based upon the updated power intent data;

generating simulation stimuli based upon the updated power state graph; and

simulating the power design utilizing the generated simulation stimuli.

2. The method of claim 1 further comprising:

selecting an ordered list of a plurality of power mode transitions;

matching the plurality of power mode transitions to one or more of the plurality of power mode transitions conditions;

selecting one or more of a plurality of input signals that correspond to the matched one or more power mode transition conditions; and

generating additional simulation stimuli based upon the selected one or more input signals.

3. The method of claim 1 further comprising:

selecting an ordered list of a plurality of power mode transitions;

determining whether the ordered list of the plurality of power mode transitions is valid compared to the updated power state graph;

in response to determining that the ordered list of the plurality of power mode transitions is valid, verifying that an existing assertion verifies execution of the selected ordered list of the plurality of power mode transitions; and

in response to determining that the ordered list of the plurality of power mode transitions is invalid, generating an assertion that monitors execution of the selected ordered list of the plurality of power mode transitions.

4. The method of claim 1 wherein the simulation utilizes an RTL file to simulate the power design, the method further comprising:

determining that the power design fails the simulation; and

modifying the RTL file in response to the failed simulation.

5. The method of claim 4 wherein the RTL file includes a plurality of processors that each correspond to the plurality of power modes included in the power intent data.

6. An information handling system comprising:

one or more processors;

a memory coupled to at least one of the processors;

a set of computer program instructions stored in the memory and executed by at least one of the processors in order to perform actions of:

generating a power state graph based upon power intent data of a power design, wherein the power state graph comprises a plurality of edges based upon a plurality of power mode transition conditions included in the power intent data to transition between one or more of a plurality of power modes of the power design;

updating the power intent data to include one or more new power mode transition conditions in response to determining that a transition sequence comprising one or more of the plurality of edges fails to exist in the power state graph from a selected first power mode to a selected second power mode, the selected first power mode and the selected second power mode included in the plurality of power modes;

generating an updated power state graph based upon the updated power intent data;

generating simulation stimuli based upon the updated power state graph; and

simulating the power design utilizing the generated simulation stimuli.

7. The information handling system of claim 6 wherein the one or more processors perform additional actions comprising:

selecting an ordered list of a plurality of power mode transitions;

matching the plurality of power mode transitions to one or more of the plurality of power mode transitions conditions;

selecting one or more of a plurality of input signals that correspond to the matched one or more power mode transition conditions; and

generating additional simulation stimuli based upon the selected one or more input signals.

8. The information handling system of claim 6 wherein the one or more processors perform additional actions comprising:

selecting an ordered list of a plurality of power mode transitions;

determining whether the ordered list of the plurality of power mode transitions is valid compared to the updated power state graph;

in response to determining that the ordered list of the plurality of power mode transitions is valid, verifying that an existing assertion verifies execution of the selected ordered list of the plurality of power mode transitions; and

in response to determining that the ordered list of the plurality of power mode transitions is invalid, generating an assertion that monitors execution of the selected ordered list of the plurality of power mode transitions.

9. The information handling system of claim 6 wherein the simulation utilizes an RTL file to simulate the power design, the one or more processors performing additional actions comprising:

determining that the power design fails the simulation; and

modifying the RTL file in response to the failed simulation.

10. A computer program product for simulating a power design, the computer program product comprising:

a non-transitory computer readable storage medium;

first program instructions to generate a power state graph based upon power intent data of a power design, wherein the power state graph comprises a plurality of edges based upon a plurality of power mode transition conditions included in the power intent data to transition between one or more of a plurality of power modes of the power design;

second program instructions to update the power intent data to include one or more new power mode transition conditions in response to determining that a transition sequence comprising one or more of the plurality of edges fails to exist in the power state graph from a selected first power mode to a selected second power mode, the selected first power mode and the selected second power mode included in the plurality of power modes;

fourth program instructions to generate an updated power state graph based upon the updated power intent data;

fifth program instructions to generate simulation stimuli based upon the updated power state graph;

sixth program instructions to simulate the power design utilizing the generated simulation stimuli; and

wherein the first, second, third, fourth, fifth, and sixth program instructions are stored on the computer readable storage medium.

11. The computer program product of claim 10 further comprising additional program instructions stored on the computer readable storage medium to perform actions of:

selecting an ordered list of a plurality of power mode transitions;

matching the plurality of power mode transitions to one or more of the plurality of power mode transitions conditions;

selecting one or more of a plurality of input signals that correspond to the matched one or more power mode transition conditions; and

generating additional simulation stimuli based upon the selected one or more input signals.

12. The computer program product of claim 10 further comprising additional program instructions stored on the computer readable storage medium to perform actions of:

selecting an ordered list of a plurality of power mode transitions;

determining whether the ordered list of the plurality of power mode transitions is valid compared to the updated power state graph;

in response to determining that the ordered list of the plurality of power mode transitions is valid, verifying that an existing assertion verifies execution of the selected ordered list of the plurality of power mode transitions; and

in response to determining that the ordered list of the plurality of power mode transitions is invalid, generating an assertion that monitors execution of the selected ordered list of the plurality of power mode transitions.

13. The computer program product of claim 10 wherein the simulation utilizes an RTL file to simulate the power design, the computer program product further comprising additional program instructions stored on the computer readable storage medium to perform actions of:

determining that the power design fails the simulation; and

modifying the RTL file in response to the failed simulation.

14. The computer program product of claim 10 wherein the RTL file includes a plurality of processors that each correspond to the plurality of power modes included in the power intent data.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0575 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0555 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0535 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0479 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 22, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030258/0501 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030256/0706 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: FENG, XIUSHAN; BHADRA, JAYANTA; LITTLE, SCOTT R.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 028149/0309 →
Continuity (1)
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