Semiconductor device manufacturing methods and methods of forming insulating material layers
Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
1. A method of forming a semiconductor device, the method comprising:
providing a workpiece;
forming a first sub-layer of a gate dielectric layer over the workpiece using a first plasma power level;
forming a second sub-layer of the gate dielectric layer over the first sub-layer of the gate dielectric layer using a second plasma power level different from the first plasma power level; and
annealing the workpiece after the forming the second sub-layer of the gate dielectric layer and while the second sub-layer of the gate dielectric layer is free of overlying layers wherein the annealing improves a material of the gate dielectric layer, removes charge caused by plasma processes used during the forming the first sub-layer or the forming the second sub-layer, and improves the interface quality of the gate dielectric layer.
2. The method according to claim 1 , wherein forming the first sub-layer of the gate dielectric layer comprises forming the first sub-layer of the gate dielectric layer using a first atomic layer deposition (ALD) process, and wherein forming the second sub-layer of the gate dielectric layer comprises forming the second sub-layer of the gate dielectric layer using a second ALD process.
3. The method according to claim 1 , wherein the second plasma power level is greater than the first plasma power level.
4. The method according to claim 1 , wherein forming the first sub-layer of the gate dielectric layer comprises using a low temperature atomic layer deposition (ALD) process without plasma.
5. The method according to claim 1 , wherein forming the first sub-layer of the gate dielectric layer comprises forming a first oxide layer, and wherein forming the second sub-layer of the gate dielectric layer comprises forming a second oxide layer.
6. The method according to claim 1 , wherein the annealing the workpiece comprises annealing the workpiece in a nitrogen environment, annealing the workpiece in an oxygen environment, or annealing the workpiece using an in-situ steam generation (ISSG) treatment; and
forming a gate electrode over the second sub-layer of the gate dielectric layer;
wherein the forming the gate electrode is performed after the annealing.
7. The method according to claim 1 , wherein annealing the workpiece comprises annealing the workpiece in a nitrogen environment, and wherein annealing the workpiece comprises forming a third sub-layer of the gate dielectric layer over the second sub-layer of the gate dielectric layer.
8. The method according to claim 7 , wherein forming the third sub-layer of the gate dielectric layer comprises forming a layer of silicon oxynitride.
9. The method according to claim 1 , further comprising performing a plasma treatment after forming the first sub-layer of the gate dielectric layer, and before forming the second sub-layer of the gate dielectric layer.
10. The method according to claim 9 , wherein performing the plasma treatment comprises using a nitrogen or oxygen plasma treatment.
11. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece, the workpiece including at least one Fin field effect transistor (FinFET) fin disposed on a surface thereof; and
forming a gate dielectric over the at least one FinFET fin using a first atomic layer deposition (ALD) process, a second ALD process, and an anneal process, wherein the second ALD process comprises a different plasma power than a plasma power of the first ALD process.
12. The method according to claim 11 , wherein forming the gate dielectric over the at least one FinFET fin using the first ALD process and the second ALD process comprises forming a first gate dielectric layer with the first ALD process over the at least one FinFET fin and forming a second gate dielectric layer with the second ALD process over the first gate dielectric layer, wherein forming the gate dielectric over the at least one FinFET fin further comprises using a second ALD process comprising a high power plasma ALD process, and wherein the second ALD process increases a density of the first gate dielectric layer.
13. The method according to claim 12 , wherein forming the first gate dielectric layer comprises forming a first oxide layer, wherein forming the second gate dielectric layer comprises forming a second oxide layer, wherein the second ALD process improves an oxide quality of the first oxide layer, and wherein the second ALD process produces a second oxide layer comprising a high quality oxide.
14. The method according to claim 12 , wherein forming the gate dielectric over the at least one FinFET fin using the anneal process improves a film quality at an interface of a surface of the FinFET fin and the first gate dielectric layer.
15. The method according to claim 11 , wherein the providing the workpiece comprises providing a workpiece wherein the at least one FinFET fin comprises at least a portion of an electrode of a transistor.
16. The method according to claim 15 , further comprising forming a gate electrode over the gate dielectric.
17. A method of manufacturing a semiconductor device, the method comprising:
providing a workpiece;
forming at least one Fin field effect transistor (FinFET) fin over the workpiece;
forming a gate dielectric over the at least one FinFET fin using a first atomic layer deposition (ALD) process, a second ALD process, and an anneal process, the second ALD process comprising a different plasma power level than a plasma power level of the first ALD process; and
forming a gate electrode over the gate dielectric, wherein the at least one FinFET fin, the gate dielectric, and the gate electrode comprise a FinFET device.
18. The method according to claim 17 , wherein forming the gate dielectric further comprises forming a thin thermal oxide layer over the at least one FinFET fin, before using the first ALD process.
19. The method according to claim 17 , wherein forming the gate dielectric comprises using a first ALD process comprising a plasma power level of about 50 Watts or less, or wherein forming the gate dielectric comprises using a second ALD process comprising a plasma power level of about 100 Watts or greater.
20. The method according to claim 17 , wherein forming the gate dielectric further comprises forming a high k dielectric material over the at least one FinFET fin, after the anneal process.