IP Library Granted Patent US 9,040,832
Granted Patent B2
US 9,040,832 · App. 13/433,680 · Granted May 26, 2015

Wiring substrate and method of manufacturing the same

Inventors: Yuichiro Shimizu (Nagano, JP); Ryo Fukasawa (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L23/49822H05K3/388H05K3/386H05K1/09H05K3/108H05K3/389H05K3/4644H05K2203/0338H01L21/4857H01L2224/16225H01L2224/32225H01L2224/73204H01L2924/15311
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Quick Facts
Patent No.
US 9,040,832
App. No.
13/433,680
Granted
May 26, 2015
Kind
B2
Abstract

A method of manufacturing a wiring substrate, includes obtaining a laminated body in which a first copper tin alloy layer and a copper layer are arranged in sequence on a first coupling agent layer, on a first insulating resin layer, forming a seed layer on the copper layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a metal plating layer in the opening portion of the plating resist by applying an electroplating that utilizes the seed layer as a plating power feeding path, removing the plating resist, and forming a first wiring layer on the first coupling agent layer by etching the seed layer, the copper layer, and the first copper tin alloy layer while using the metal plating layer as a mask.

Claims (20)

1. A wiring substrate, comprising:

a first insulating resin layer;

a first coupling agent layer formed on the first insulating resin layer;

a first wiring layer including a first copper tin alloy layer formed on the first coupling agent layer, a copper layer formed on the first copper tin alloy layer, a seed layer formed on the copper layer, and a metal plating layer formed on the seed layer; and

an underlayer wiring layer formed under the first insulating resin layer, a via hole being formed in the first insulating resin layer to reach the underlayer wiring layer,

wherein the first coupling agent layer is formed on the first insulating resin layer except the via hole, and

wherein the seed layer is formed to extend from an inner surface of the via hole onto the copper layer, and

the first wiring layer is connected to the underlayer wiring layer via the via hole.

2. A wiring substrate according to claim 1 , further comprising:

a second copper tin alloy layer formed on an upper surface and a side surface of the first wiring layer;

a second coupling agent layer covering the second copper tin alloy layer of the first wiring layer; and

a second insulating resin layer formed on the second coupling agent layer.

3. A wiring substrate according to claim 2 , further comprising:

a via hole formed in the second insulating resin layer, the second coupling agent layer, and the second copper tin alloy layer to reach the first wiring layer; and

a second wiring layer formed on the second insulating resin layer, and connected to the first wiring layer via the via hole.

4. A wiring substrate according to claim 3 , further comprising:

a third copper tin alloy layer formed on an upper surface and a side surface of the second wiring layer;

a third coupling agent layer covering the third copper tin alloy layer of the second wiring layer; and

a protection insulating layer formed on the third coupling agent layer, and in which an opening portion is provided in a part corresponding to a connection part of the second wiring layer;

wherein the third coupling agent layer and the third copper tin alloy layer located in the opening portion of the protection insulating layer are removed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2015
From: SHIMIZU, YUICHIRO; FUKASAWA, RYO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 034861/0290 →
Priority Claims (2)
JP 2011-072694 · Mar 29, 2011 · national
JP 2012-015679 · Jan 27, 2012 · national
Continuity (1)
Related Publication 20120247814A1 · Oct 4, 2012