Inhibiting pillars in 3D memory devices
Methods and controllers for programming a memory are provided. In one such method, a potential for pillars of the memory that are to be inhibited is lowered, and programming cells of the memory is accomplished while the pillars of the memory that are to be inhibited have the lower potential.
1. A method of inhibiting programming of a memory cell corresponding to a pillar of semiconductor material, comprising:
increasing a voltage on the pillar corresponding to the memory cell to be inhibited from programming without increasing a voltage on a pillar corresponding to a memory cell to be enabled for programming; and
after increasing the voltage on the pillar, boosting the voltage on the pillar corresponding to the memory cell to be inhibited from programming prior to applying a program pulse on a control gate coupled to the memory cell to be inhibited from programming and the memory cell to be enabled for programming;
wherein increasing the voltage on the pillar comprises decreasing a voltage on a select device corresponding to the pillar corresponding to the memory cell to be inhibited from programming from a first voltage to a second voltage while a data line coupled to the select device is at an inhibit voltage.
2. The method of claim 1 , wherein increasing a voltage comprises increasing a voltage from a reference voltage (Vss) to a +Vpillar voltage.
3. The method of claim 2 , wherein boosting the voltage comprises boosting the voltage from the +Vpillar voltage to an inhibit voltage.
4. The method of claim 1 , wherein increasing the voltage on the pillar lowers a threshold voltage of the memory cell to be inhibited from programming.
5. The method of claim 1 , wherein increasing the voltage on the pillar increases channel boosting efficiency of the pillar.
6. The method of claim 1 , wherein boosting the voltage on the pillar after increasing the voltage on the pillar boosts the voltage higher than if the voltage on the pillar was boosted without first increasing the voltage on the pillar.
7. The method of claim 1 , wherein select device is a drain select transistor.
8. A method of inhibiting programming of a memory cell corresponding to a pillar of semiconductor material, comprising:
increasing a voltage on the pillar corresponding to the memory cell to be inhibited from programming without increasing a voltage on a pillar corresponding to a memory cell to be enabled for programming; and
after increasing the voltage on the pillar, boosting the voltage on the pillar corresponding to the memory cell to be inhibited from programming prior to applying a program pulse on a control gate coupled to the memory cell to be inhibited from programming and the memory cell to be enabled for programming;
wherein increasing a voltage on the pillar comprises generating GIDL current at a select device corresponding to the pillar corresponding to the memory cell to be inhibited from programming.
9. A method of inhibiting programming of a memory cell corresponding to a pillar of semiconductor material, comprising:
generating gate induced drain leakage (GIDL) current at a select device corresponding to the pillar to increase a voltage on the pillar; and
after generating the GIDL current, boosting the voltage on the pillar prior to applying a program pulse on a control gate coupled to a memory cell corresponding to the pillar.
10. The method of claim 9 , wherein boosting the voltage on the pillar comprises applying a Vpass_program voltage to control gates of the memory cells corresponding to the pillar.
11. The method of claim 10 , wherein boosting the voltage on the pillar further comprises applying a voltage Vcc+ to the control gates before applying Vpass_program.
12. The method of claim 9 , wherein increasing the voltage on the pillar lowers a threshold voltage of the memory cell to be inhibited from programming.
13. The method of claim 9 , wherein increasing the voltage on the pillar increases channel boosting efficiency of the pillar.
14. The method of claim 9 , wherein boosting the voltage on the pillar after increasing the voltage on the pillar boosts the voltage higher than if the voltage on the pillar was boosted without first increasing the voltage on the pillar.
15. The method of claim 9 , wherein generating GIDL current comprises:
biasing a data line coupled to the pillar through the select device to a supply voltage (Vcc); and
biasing a control gate of the select device to a −Vgidl voltage.
16. The method of claim 9 , generating GIDL current at a select device comprises increasing the voltage on the pillar from a reference voltage to a +Vpillar voltage and wherein boosting the voltage on the pillar comprises boosting the voltage from the +Vpillar voltage to an inhibit voltage.
17. A method of inhibiting programming of a memory cell corresponding to a pillar of semiconductor material, comprising:
increasing a voltage on the pillar by impact ionization; and
after increasing the voltage, boosting the voltage on the pillar prior to applying a program pulse on a control gate coupled to a memory cell corresponding to the pillar;
wherein increasing the voltage on the pillar by impact ionization comprises increasing a voltage on a select device corresponding to the pillar from a first voltage to a second voltage while a data line coupled to the select device is at an inhibit voltage; and
wherein the voltage on the select device corresponding to the pillar is decreased from the second voltage to the first voltage and increased from the first voltage to a third voltage greater than the second voltage before boosting the voltage on the pillar.
18. The method of claim 17 , wherein the inhibit voltage is a supply voltage and the second voltage is ½ the supply voltage.
19. The method of claim 17 , wherein increasing a voltage on the pillar comprises increasing the voltage from a reference voltage to a +Vpillar voltage and wherein boosting the voltage on the pillar comprises boosting the voltage from the +Vpillar voltage to an inhibit voltage.
20. The method of claim 17 , wherein increasing the voltage on the pillar lowers a threshold voltage of the memory cell to be inhibited from programming.
21. The method of claim 17 , wherein increasing the voltage on the pillar increases channel boosting efficiency of the pillar.
22. The method of claim 17 , wherein boosting the voltage on the pillar after increasing the voltage on the pillar boosts the voltage higher than if the voltage on the pillar was boosted without first increasing the voltage on the pillar.
23. The method of claim 17 , wherein third voltage is greater than the inhibit voltage.
24. A memory device, comprising:
an array of memory cells; and
a controller, the controller adapted to perform a method comprising:
increasing a voltage on the pillar corresponding to the memory cell to be inhibited from programming without increasing a voltage on a pillar corresponding to a memory cell to be enabled for programming; and
after increasing the voltage on the pillar, boosting the voltage on the pillar corresponding to the memory cell to be inhibited from programming prior to applying a program pulse on a control gate coupled to the memory cell to be inhibited from programming and the memory cell to be enabled for programming;
wherein increasing the voltage on the pillar comprises decreasing a voltage on a select device corresponding to the pillar corresponding to the memory cell to be inhibited from programming from a first voltage to a second voltage while a data line coupled to the select device is at an inhibit voltage.
25. The memory device of claim 24 , wherein the controller is further adapted to increase a voltage comprises increasing a voltage from a reference voltage (Vss) to a +Vpillar voltage.
26. The memory device of claim 25 , wherein boosting the voltage comprises boosting the voltage from the +Vpillar voltage to an inhibit voltage.
27. A memory device, comprising:
an array of memory cells; and
a controller, the controller adapted to perform a method comprising:
increasing a voltage on the pillar corresponding to the memory cell to be inhibited from programming without increasing a voltage on a pillar corresponding to a memory cell to be enabled for programming; and
after increasing the voltage on the pillar, boosting the voltage on the pillar corresponding to the memory cell to be inhibited from programming prior to applying a program pulse on a control gate coupled to the memory cell to be inhibited from programming and the memory cell to be enabled for programming;
wherein the controller is further adapted to increase a voltage on the pillar by generating GIDL current at a select device corresponding to the pillar corresponding to the memory cell to be inhibited from programming.
28. A memory device, comprising:
an array of memory cells; and
a controller, the controller adapted to perform a method comprising:
generating gate induced drain leakage (GIDL) current at a select device corresponding to the pillar to increase a voltage on the pillar; and
after generating the GIDL current, boosting the voltage on the pillar prior to applying a program pulse on a control gate coupled to a memory cell corresponding to the pillar.
29. A memory device comprising:
an array of memory cells; and
a controller, the controller adapted to perform a method comprising:
increasing a voltage on the pillar by impact ionization; and
after increasing the voltage, boosting the voltage on the pillar prior to applying a program pulse on a control gate coupled to a memory cell corresponding to the pillar;
wherein increasing the voltage on the pillar by impact ionization comprises increasing a voltage on a select device corresponding to the pillar from a first voltage to a second voltage while a data line coupled to the select device is at an inhibit voltage; and
wherein the voltage on the select device corresponding to the pillar is decreased from the second voltage to the first voltage and increased from the first voltage to a third voltage greater than the second voltage before boosting the voltage on the pillar.