Elongated bump structure in semiconductor device
A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d 1 ) measured along the long axis of the conductive pillar and a second dimension (d 2 ) measured along the short axis of the conductive pillar. A ratio of L to d 1 is greater than a ratio of W to d 2.
1. A device, comprising:
a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar; and
a substrate comprising a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace,
wherein the chip is attached to the substrate to form an interconnection between the conductive pillar and the exposed portion of the conductive trace, and
wherein the opening has a first dimension (d 1 ) measured along the long axis of the conductive pillar and a second dimension (d 2 ) measured along the short axis of the conductive pillar, and a ratio of L to d 1 is greater than a ratio of W to d 2 .
2. The device of claim 1 , wherein a ratio of L to d 1 ranges from 1.05 to 2.0.
3. The device of claim 1 , wherein a ratio of W to d 2 ranges from 0.8 to 1.3.
4. The device of claim 1 , wherein the conductive pillar has an elongated shape.
5. The device of claim 1 , further comprising a solder joint region between the conductive pillar and the exposed portion of the conductive trace.
6. The device of claim 1 , wherein the mask layer is formed of a solder resist material layer.
7. The device of claim 1 , wherein the conductive pillar comprises copper.
8. The device of claim 1 , wherein the conductive trace comprises copper.
9. The device of claim 1 , wherein the long axis of the conductive pillar is perpendicular to an edge of the chip.
10. The device of claim 1 , wherein the long axis of the conductive pillar is along a direction toward a central area of the chip.
11. A device, comprising:
a conductive pillar formed on a first substrate, the conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar;
a conductive trace formed on a second substrate; and
a mask layer overlying the conductive trace and the second substrate, the mask layer having an opening exposing a portion of the conductive trace,
wherein the conductive pillar is connected to the exposed portion of the conductive trace through a solder layer, and
wherein the opening of the mask layer has a first dimension (d 1 ) measured along the long axis of the conductive pillar, and d 1 is less than L.
12. The device of claim 11 , wherein a ratio of L to d 1 ranges from 1.05 to 2.0.
13. The device of claim 11 , wherein the opening of the mask layer has a second dimension (d 2 ) measured along the short axis of the conductive pillar, and a ratio of W to d 2 ranges from 0.8 to 1.3.
14. The device of claim 11 , wherein the conductive pillar has an elongated shape.
15. The device of claim 11 , wherein the mask layer is formed of a solder resist material layer.
16. The device of claim 11 , wherein the conductive pillar comprises copper.
17. The device of claim 11 , wherein the conductive trace comprises copper.
18. The device of claim 11 , wherein the first substrate is a semiconductor substrate, and the second substrate is a dielectric substrate.
19. A device, comprising:
a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar; and
a substrate comprising a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace,
wherein the chip is attached to the substrate to form an interconnection between the conductive pillar and the exposed portion of the conductive trace, and
wherein the opening has a first dimension (d 1 ) measured along the long axis of the conductive pillar and a second dimension (d 2 ) measured along the short axis of the conductive pillar, and a ratio of L to d 1 is not equal to a ratio of W to d 2 .
20. The device of claim 19 , wherein a ratio of L to d 1 ranges from 1.05 to 2.0.