3D integrated circuit structure, semiconductor device and method of manufacturing same
View Patent ↗The present invention discloses a semiconductor device. In one embodiment, the semiconductor device comprises a substrate, a diffusion stop layer formed on the substrate, an SOI layer formed on the diffusion stop layer, an MOSFET transistor formed on the SOI layer, and a TSV formed in a manner of penetrating through the substrate, the diffusion stop layer, the SOI layer, and a layer where the MOSFET transistor is located; and an interconnect structure connecting the MOSFET transistor and the TSV.
1. A three-dimension integrated circuit structure, characterized in that the integrated circuit structure comprises:
a first wafer, comprising:
a substrate defining a contact surface of the first wafer;
a layer having a metal oxide semiconductor field effect transistor (MOSFET) formed therein;
a diffusion stop layer disposed between the substrate and the layer having the MOSFET transistor;
a silicon-on-insulator (SOI) layer formed on the diffusion stop layer;
a through-silicon-via (TSV) formed in a manner of penetrating through the substrate, the diffusion stop layer, the SOI layer and at least partially penetrating through the layer having the MOSFET transistor; and
a first interconnect structure for connecting the MOSFET transistor and the TSV;
wherein a metal material filled in the TSV is exposed at the contact surface of the first wafer, the TSV further comprises a buried layer positioned between the surface of the TSV and the metal material, and the contact surface of the first wafer is connected to external circuits or a second interconnect structure of a second wafer by means of the TSV.
2. The integrated circuit structure according to claim 1 , characterized in that the diffusion stop layer is formed of nitride.
3. The integrated circuit structure according to claim 2 , characterized in that the nitride comprises Si3N4 or SiCN.
4. The integrated circuit structure according to claim 1 , characterized in that the first wafer further comprises a first oxide layer formed between the substrate and the diffusion stop layer.
5. The integrated circuit structure according to claim 1 , characterized in that the first wafer further comprises a second oxide layer formed between the diffusion stop layer and the SOI layer.
6. The integrated circuit structure according to claim 1 , characterized in that the buried layer comprises at least a material selected from a group comprising Ru, Ta, TaN, Ti, TiN, TaSiN, TiSiN, TiW and WN.
7. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate defining a contact surface of the semiconductor device;
a layer having a metal oxide semiconductor field effect transistor (MOSFET) formed therein;
a diffusion stop layer formed between the substrate and the layer having the MOSFET transistor;
an SOI layer formed on the diffusion stop layer;
a TSV formed in a manner of penetrating through the substrate, the diffusion stop layer, the SOI layer and at least partially penetrating through the layer having the MOSFET transistor; and
an interconnect structure for connecting the MOSFET transistor and the TSV;
wherein a metal material filled in the TSV is exposed at the contact surface of the semiconductor device, the TSV further comprises a buried layer positioned between the surface of the TSV and the metal material.
8. The semiconductor device according to claim 7 , characterized in that the diffusion stop layer is formed of nitride.
9. The semiconductor device according to claim 8 , characterized in that the nitride comprises Si3N4 or SiCN.
10. The semiconductor device according to claim 7 , characterized by further comprising a first oxide layer formed between the substrate and the diffusion stop layer.
11. The semiconductor device according to claim 7 , characterized by further comprising a second oxide layer formed between the diffusion stop layer and the SOI layer.
12. The integrated circuit structure according to claim 1 , wherein the layer having the MOSFET transistor defines another contact surface of the first wafer.
13. The integrated circuit structure according to claim 1 , wherein the first interconnect structure is formed in the layer having the MOSFET transistor.
14. The integrated circuit structure according to claim 13 , wherein the first interconnect structure is configured to connect the first wafer to another wafer.
15. The semiconductor device according to claim 7 , wherein the layer having the MOSFET transistor defines another contact surface of the semiconductor device.
16. The semiconductor device according to claim 7 , wherein the interconnect structure is formed in the layer having the MOSFET transistor.