IP Library › Granted Patent US 9,069,661
Granted Patent B2
US 9,069,661 · App. 14/092,731 · Granted Jun 30, 2015

Control arrangements and methods for accessing block oriented nonvolatile memory

Inventor: Stephen P. Van Aken (Boulder, CO)
Assignee: Micron Technology, Inc.
G06F12/0246Y02B60/1225
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Quick Facts
Patent No.
US 9,069,661
App. No.
14/092,731
Granted
Jun 30, 2015
Kind
B2
Abstract

A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes a plurality of modules, each module including a nonvolatile memory section. In one feature, at least a particular one of the modules is configured to independently maintain a module portion of a distributed flash translation layer for the nonvolatile memory section of only that particular module based on one or more module input parameters. In another feature, a particular module defines an independent execution of at least one of a wear leveling function, a garbage collection function and a bit density function. Associated methods are described.

Claims (36)

1. A memory system for digital data communication with a host device to provide data storage capacity for the host device, said memory system comprising:

a plurality of modules, each module including a nonvolatile memory section, wherein at least a particular one of the modules is configured to independently maintain a module portion of a distributed flash translation layer for the nonvolatile memory section of only that particular module based on one or more module input parameters.

2. The memory system of claim 1 , further comprising:

a controller configured for digital data communication with the host device and further configured for module digital data communication with each of the plurality of modules such that any data flowing to and from the particular module passes through the controller, wherein the controller is configured to provide the one or more module input parameters to the particular module to define an independent execution of the module portion of the distributed flash translation layer.

3. The memory system of claim 1 , further comprising:

a controller configured to provide the module input parameters to the particular module and wherein the particular module further comprises a flash translation layer parameter section that is configured to receive a first set of flash translation layer parameters from the controller for controlling the independent execution of the module portion of the distributed flash translation layer in a first mode.

4. The memory system of claim 3 wherein the flash translation layer parameter section is further configured to receive a second set of flash translation layer parameters from the particular module for controlling the independent execution of the module portion of the distributed flash translation layer in a second mode.

5. The memory system of claim 1 , further comprising:

a controller configured to provide the module input parameters to the particular module and wherein the particular module is further configured to selectably operate in a first mode such that the particular module autonomously executes the flash translation layer and to selectably operate in a second mode under at least partial control by the controller such that the particular module executes the flash translation layer in cooperation with the controller.

6. The memory system of claim 1 wherein the particular module further comprises:

a function engine for independently performing at least one of a wear leveling function, a garbage collection function and a bit density setting function for the nonvolatile memory section of only the particular module.

7. The memory system of claim 6 wherein said function engine further comprises a reporting section for reporting one or more use statistics relating to the nonvolatile memory of the particular module such that the use statistics are available to at least the function engine.

8. The memory system of claim 7 wherein read-back values are generated by the reporting section responsive to a read operation and wherein the use statistics include at least one of a mean read-back value for at least a set of read values during the read operation and a standard deviation for read-back values for at least the set of read values during the read operation and one or more error correction statistics.

9. The memory system of claim 8 wherein the one or more error correction statistics include at least one of a cumulative error count and a per block error count based on the read operation decoding a block error correction code.

10. The memory system of claim 7 wherein the reporting section is configured to provide a health indication relating to the nonvolatile memory based on the use statistics.

11. A module serving as one of a plurality of modules as part of a memory system for digital data communication with a host device to provide data storage capacity for the host device, said module comprising:

a nonvolatile memory section; and

a function engine configured to independently maintain a module portion of a distributed flash translation layer for the nonvolatile memory section of only that module based on one or more module input parameters.

12. A method for use in a module serving as one of a plurality of modules as part of a memory system for digital data communication with a host device to provide data storage capacity for the host device, said method comprising:

within the module, independently maintaining a module portion of a distributed flash translation layer for a nonvolatile memory section of only that module based on one or more module input parameters.

13. A memory system for digital data communication with a host device to provide data storage capacity for the host device, said memory system comprising:

a plurality of modules, each module including a nonvolatile memory section, wherein at least a particular one of the modules is configured to independently perform an error correction function in conjunction with independently performing at least one of a wear leveling function, a garbage collection function and a bit density setting function for the nonvolatile memory section of only the particular module based on one or more module input parameters; and

a controller configured for said digital data communication with the host device and further configured for module digital data communication with each of the plurality of modules such that any data flowing to and from each module passes through the controller and at least the controller is configured to provide the module input parameters to the particular module to define an independent execution of at least one of the wear leveling function, the garbage collection function and the bit density function in the particular module.

14. The memory system of claim 13 wherein the particular module further comprises:

a function engine for independently performing the error correction function and at least one of the wear leveling function, the garbage collection function and a bit density setting function for the nonvolatile memory section of only the particular module.

15. The memory system of claim 14 wherein said function engine further comprises a reporting section for reporting one or more use statistics relating to the nonvolatile memory of the particular module such that the use statistics are available to at least the function engine.

16. The memory system of claim 15 wherein the reporting section is configured to provide a health indication relating to the nonvolatile memory based on the use statistics.

17. The memory system of claim 13 wherein the particular module is configured to operate at least in a first mode at least for a selected one of the wear leveling function, the garbage collection function and the bit density setting function based on a first set of the one or more module input parameters and to operate in a second mode for the selected one of the functions based on a second set of the one or more module input parameters with the first set of module input parameters being different from the second set of module input parameters.

18. The memory system of claim 17 wherein at least the particular module is further configured to independently execute a flash translation layer only for the nonvolatile memory section of the particular module.

19. The memory system of claim 13 , further comprising:

the particular module further configured to selectably operate in a first mode such that the particular module autonomously executes a flash translation layer and selectably operates in a second mode under at least partial control by the controller such that the particular module executes the flash translation layer in cooperation with the controller.

20. A module serving as one of a plurality of modules as part of a memory system for digital data communication with a host device to provide data storage capacity for the host device, said module comprising:

a nonvolatile memory section; and

a function engine that is configured to independently perform an error correction function in conjunction with independently performing at least one of a wear leveling function, a garbage collection function and a bit density setting function for the nonvolatile memory section of only that module based on one or more module input parameters.

21. A method for use in a module serving as one of a plurality of modules as part of a memory system for digital data communication with a host device to provide data storage capacity for the host device, said method comprising:

within the module, independently performing an error correction function in conjunction with independently performing at least one of a wear leveling function, a garbage collection function and a bit density setting function for the nonvolatile memory section of only that module based on one or more module input parameters.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2013
From: VAN AKEN, STEPHEN P.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 031689/0048 →
Continuity (2)
Continuation 13019969 · Feb 2, 2011
Related Publication 20140156916A1 · Jun 5, 2014