Granted Patent B2

US 9,088,303 · App. 13/780,726 · Granted Jul 21, 2015

Inventors: Troy D. Larsen (Meridian, ID); Martin L. Culley (Boise, ID)

Assignee: Micron Technology, Inc.

H03M13/2906H03M13/09H03M13/1102H03M13/152H03M13/1515

Abstract

Claims (115)

1. A method, comprising:

writing:

a first portion of a first primary codeword to a first page in a first block of memory;

a second portion of the first primary codeword to a second page in a second block of memory; and

a first portion and a second portion of a second primary codeword to the first page in the first block of memory;

including the first primary codeword in a first secondary codeword and the second primary codeword in a second secondary codeword;

testing a number of blocks including the first block and the second block; and

when the first block of memory and the second block of memory are good blocks of memory, writing:

a first portion of the first secondary codeword in the memory; and

a second portion of the first secondary codeword to a different page and block of the memory than the first portion of the first secondary codeword; and

a first portion and a second portion of the second secondary codeword in the memory; and

when the second block of memory is a bad block of memory:

writing neither the first portion nor the second portion of the first secondary codeword to the memory; and

writing the first portion and the second portion of the second secondary codeword to the memory.

2. The method of claim 1 , wherein including the first primary codeword in the first secondary codeword comprises mirroring the first primary codeword as the first secondary codeword.

3. The method of claim 1 , wherein including the first primary codeword in the first secondary codeword comprises error coding the first primary codeword and at least one other primary codeword as the first secondary codeword.

4. The method of claim 3 , wherein the method comprises calculating error data based on the first primary codeword and the at least one other primary codeword; and

wherein the first and the second portion of the first secondary codeword comprise the error data.

5. The method of claim 1 , wherein writing the first portion of the first secondary codeword comprises writing the first portion of the first secondary codeword to a third page in a third block of memory; and

wherein writing the second portion of the first secondary codeword comprises writing the second portion of the first secondary codeword to a fourth page in a fourth block of memory.

6. The method of claim 1 , wherein the method comprises:

error coding data comprising the first primary codeword prior to writing the first and the second portions of the first primary codeword; and

error coding at least a portion of the first secondary codeword as a second primary codeword comprising the first and the second portions of the first secondary codeword.

7. The method of claim 6 , wherein error coding data comprising the first primary codeword comprises one or more of the group including:

cyclic redundancy check (CRC) coding;

Bose-Chaudhuri-Hocquenghem (BCH) coding; and

low density parity check (LDPC) coding; and

wherein the method comprises error coding the primary codeword and at least one other primary codeword as the secondary codeword using one of the group of coding schemes including:

performing an exclusive or (XOR) operation on the primary codeword and the at least one other primary codeword;

Reed-Solomon error coding; and

BCH coding.

8. A method, comprising:

error coding data as a plurality of primary codewords;

writing a first group of primary codewords of the plurality of primary codewords to a plurality of pages of memory such that the first group of primary codewords each span at least two of the plurality of pages of the memory;

writing a second group of primary codewords of the plurality of primary codewords to one of the at least two of the plurality of pages of the memory;

error coding;

at least one of the first group of the plurality of primary codewords as a first secondary codeword; and

at least one of the second group of primary codewords as a second secondary codeword;

wherein the error coding includes:

writing the second secondary codeword when the one of the at least two of the plurality of pages the second group of primary codewords is written to is in a good block of memory;

not writing the second secondary codeword when the one of the at least two of the plurality of pages is in a bad block of memory;

not writing the first secondary codeword when one of the at least two of the plurality of pages the first group of primary codewords is written on is in an indicated good block of memory and an other one of the at least two of the plurality of pages the first group of primary codewords is written on is in an indicated bad block of memory; and

writing the first secondary codeword when the at least two of the plurality of pages are written in two good blocks of memory.

9. The method of claim 8 , wherein:

error coding the at least one of the first group of the plurality of primary codewords comprises mirroring one of the first group of the plurality of primary codewords as the first secondary codeword; and

writing an entirety of the first secondary codeword to span at least two pages of memory.

10. The method of claim 9 , wherein writing the first secondary codeword to span the at least two pages of memory comprises writing the first secondary codeword to one page of memory in each of at least two different blocks of memory.

11. The method of claim 9 , wherein writing the first secondary codeword to span the at least two pages of memory comprises writing the first secondary codeword to one respective page of memory in each of at least two different memory dice.

12. A method, comprising:

error coding data as a plurality of primary codewords;

writing the plurality of primary codewords to a plurality of pages of memory;

error coding a first secondary codeword based on at least one of the plurality of primary codewords;

error coding a second secondary codeword based on at least one of the plurality of primary codewords;

writing at least a portion of the first secondary codewords to at least two pages of memory such that the portion of the first secondary codewords spans the at least two pages of memory, wherein the at least two pages of memory are in good blocks of memory; and

not writing a first portion of the second secondary codeword to a portion of a first page of memory when the corresponding first portion of the corresponding at least one of the plurality of primary codewords is in an indicated good block of memory and a corresponding second portion of the corresponding at least one of the plurality of primary codewords is in a page of memory in an indicated bad block of memory, wherein a second portion of the second secondary codeword would be written to the second page of memory if the second page of memory of the corresponding at least one of the plurality of primary codewords were in an indicated good block of memory.

13. The method of claim 12 , wherein the first portion and the second portion of the secondary codeword comprise parity data for the secondary codeword.

14. The method of claim 12 , wherein the first portion and the second portion of the secondary codeword collectively comprise a mirrored primary codeword.

15. The method of claim 12 , wherein writing the plurality of primary codewords to a plurality of pages of memory comprises writing the plurality of primary codewords such that each of the plurality of primary codewords do not span a page of memory.

16. The method of claim 12 , wherein writing the plurality of primary codewords to a plurality of pages of memory comprises writing the plurality of primary codewords such that a subset of the plurality of primary codewords each span at least two of the plurality of pages of memory.

17. The method of claim 12 , wherein writing the portion of the first secondary codeword to the at least two pages of memory comprises writing the portion of the first secondary codeword in each of a first and a second block of memory; and

wherein the first block of memory does not comprise a first particular block of memory that is indicated to be a good block of memory in a block table in response to a second particular block of memory corresponding to the first particular block of memory being indicated as a bad block of memory in the block table.

18. An apparatus, comprising:

a plurality of memory devices; and

a controller coupled to the plurality of memory devices and configured to:

maintain a correspondence between first pages of memory and second pages of memory in each of a plurality of pairs of blocks of memory, wherein each of the plurality of pairs of blocks of memory includes a first block of memory including a respective first page of memory and a second block of memory including a respective second page of memory; and

prevent writing of a portion of a first codeword to a particular first page of memory that is in an indicated good block of memory in response to a corresponding second page of memory being in an indicated bad block of memory; and

writing a second codeword to the first page of memory.

19. The apparatus of claim 18 , wherein the controller is configured to write the portion of the codeword to the particular first page of memory and a second portion of the codeword to the corresponding second page of memory in response to the first page being in an indicated good block of memory and in response to the corresponding second page being in an indicated good block of memory.

20. The apparatus of claim 18 , wherein the codeword comprises a primary codeword, and wherein the controller is configured to:

write a plurality of primary codewords, each to a respective first and corresponding second page of memory;

error code the plurality of primary codewords as a secondary codeword; and

write at least a portion of the secondary codeword to a portion of a third page of memory and a portion of a fourth page of memory.

21. The apparatus of claim 20 , wherein the controller is configured to recover one of the plurality of primary codewords that is subject to an uncorrectable error based on a remainder of the plurality of codewords and the portion of the secondary codeword, which comprises error data fro the secondary codeword.

22. The apparatus of claim 20 , wherein the at least a portion of the secondary codeword comprises and entirety of the secondary codeword, which comprises a mirrored primary codeword.

23. The apparatus of claim 18 , wherein each of the plurality of pairs of blocks of memory is on a different memory die.

24. An apparatus, comprising:

a plurality of memory devices; and

a controller coupled to the plurality of memory devices and configured to:

read a plurality of first pages of memory, wherein the plurality of first pages of memory collectively include an integer number of primary codewords, and wherein each first page of memory individually includes a non-integer number of primary codewords, wherein when a non-integer portion of a primary codeword of the number of primary codewords is in a bad block of memory all portions of the primary codeword are not written to memory;

read a second page of memory, wherein the second page of memory includes at least a portion of a secondary codeword; and

recover one of the integer number of primary codewords based on the secondary codeword.

25. The apparatus of claim 24 , wherein the controller is configured to recover the one of the integer number of primary codewords in response to a read error associated with the one of the integer number of primary codewords that cannot be corrected by error data associated only with the one of the integer number of primary codewords.

26. The apparatus of claim 24 , wherein the integer number of primary codewords each include user data and error data that is associated exclusively therewith; and

wherein the portion of the secondary codeword comprises parity data for the secondary codeword calculated based on more than one of the integer number of primary codewords.

27. The apparatus of claim 24 , wherein the at least a portion of the secondary codeword comprises an entirety of the secondary codeword, and wherein the secondary codeword comprises a mirror of the one of the integer number of primary codewords.

28. An apparatus, comprising:

a plurality of memory devices;

a secondary error control coding (ECC) component configured to:

error code a first plurality of primary codewords that each span at least two pages of memory as a first secondary codeword; and

error code a second plurality of primary codewords that each span at least two pages of memory as a second secondary codeword, wherein the second plurality of primary codewords include fewer primary codewords than the first plurality of primary codewords based on an indicated bad block of memory;

a controller coupled to the secondary ECC component and to the plurality of memory devices and configured to:

write at least a portion of the first secondary codeword to span at least two pages of memory; and

write at least a portion of the second secondary codeword to span at least two pages of memory;

wherein, when:

a first primary codeword of the first plurality of primary codewords is written to a first page and a second page of the memory;

a second primary codeword of the second plurality of primary codewords is written to the second page and a third page of the memory; and

the third page is in a bad block of memory;

the error-coded second primary codeword is not written to either of the second page and the third page while the error-coded first primary codeword is written to both the first page and the second page.

29. The apparatus of claim 28 , wherein the controller is configured to:

write each of the first plurality of primary codewords to a different one of the plurality of memory devices; and

write each of the second plurality of primary codewords to a different one of the plurality of memory devices.

30. The apparatus of claim 28 , wherein each of the first plurality of primary codewords spans at least two planes of memory; and

wherein each of the second plurality of primary codewords spans at least two planes of memory.

31. The apparatus of claim 28 , wherein the apparatus includes a block table; and

wherein the controller is configured to:

maintain the block table to include an indication of whether each block of memory is a bad block of memory;

write a particular primary codeword to span at least two particular pages of memory in response to the block table indicating that the at least two particular pages of memory are in a number of good blocks of memory; and

not write the particular primary codeword to span the at least two particular pages of memory in response to the block table indicating that either of the at least two particular pages of memory is in a bad block of memory.

32. The apparatus of claim 28 , wherein the controller is configured to:

write the first plurality of primary codewords and the portion of the first secondary codeword as a first redundant array of independent nodes (RAIN) stripe; and

write the second plurality of primary codewords and the portion of the second secondary codeword as a second RAIN stripe.

33. The apparatus of claim 28 , wherein the apparatus includes a primary ECC component configured to error code data with a fixed primary codeword size; and

wherein the plurality of memory devices have a fixed page size that is not evenly divisible by the fixed primary codeword size.

34. The apparatus of claim 33 , wherein the primary and the secondary ECC components are part of the controller.

35. The apparatus of claim 33 , wherein at least one of the primary and the secondary ECC components are separate from the controller.

Assignments (8)

Continuity (1)