Method of forming high K metal gate
View Patent ↗A semiconductor device and method of forming the same includes a substrate having a NMOS region and a PMOS region. The method includes forming a dummy gate structure having a stacked sacrificial dielectric layer and a sacrificial gate material layer on the NMOS and PMOS regions. The method further includes concurrently removing the stacked sacrificial dielectric layer and a sacrificial gate material layer to form a groove, and forming a high-K dielectric layer and a first metal gate layer in the grove. The method also includes forming a hard mask over the NMOS region, removing the first metal gate layer and the high-K dielectric layer in the PMOS region to form a channel groove, forming a second high-K dielectric layer and a second metal gate layer in the channel grove, and removing the hard mask. The work function metal layer in the NMOS and PMOS regions can be independently controlled.
1. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate having a NMOS region and a PMOS region;
forming dummy gate structures having a stacked sacrificial gate material layer over a sacrificial dielectric layer in the NMOS and PMOS regions;
concurrently removing the sacrificial gate material layer and the sacrificial dielectric layer to form a groove in the dummy gate structure in the NMOS region and a groove in the dummy gate structure in the PMOS region;
forming a first high-K dielectric layer in the grooves of the NMOS and PMOS regions and a first metal gate over the first high-K dielectric layer;
forming a hard mask over the NMOS region;
removing the first metal gate layer and the first high-K dielectric layer of the dummy gate structure in the PMOS region using the hard mask as a mask to form a channel groove in the semiconductor substrate;
forming a second high-K dielectric layer in the channel groove;
forming a second metal gate over the second high-K dielectric layer; and
removing the hard mask.
2. The method of claim 1 , wherein concurrently removing the sacrificial gate material layer and the sacrificial dielectric layer of the dummy gate structures comprises a dry-etching process.
3. The method of claim 2 , wherein the dry-etching process is characterized by a HBr etching gas at a flow rate in a range between 20 sccm and 500 sccm, a pressure in a range between 2 mTorr and 40 mTorr, and a power in a range between 100 W and 2000 W.
4. The method of claim 2 , further comprising a wet etching process to remove residues and impurities generated by the dry-etching process.
5. The method of claim 1 , wherein removing the first metal gate layer and the first high-K dielectric layer of the dummy gate structure in the PMOS region comprises a dry-etching process.
6. The method of claim 5 , wherein the dry-etching process is characterized by a mixture gas of Cl 2 and O 2 as an etching gas, a flow rate of the Cl 2 gas being in a range between 50 sccm and 500 sccm, a flow rate of the O 2 gas being in a range between 2 sccm and 10 sccm, a pressure in a range between 2 mTorr and 40 mTorr, and a power in a range between 100 W and 2000 W.
7. The method of claim 5 , wherein removing the first metal gate layer and the first high-K dielectric layer of the dummy gate structure in the PMOS region comprises a combined dry and wet etching process.
8. The method of claim 1 , wherein the channel groove has a depth in a range between 1 nm and 4 nm.
9. The method of claim 1 , further comprising, prior to removing the sacrificial dielectric layer and the sacrificial gate material layer:
forming sidewall structures on opposite sides of the dummy gate structures;
forming source/drain regions adjacent to the sidewall structures;
forming silicon germanium layers adjacent to the sidewall structures in the PMOS region;
forming a contact hole etch stop layer;
forming an interlayer dielectric layer completely covering the contact hole etch stop layer and the dummy gate structures; and
performing a chemical mechanical polishing process to expose a top surface of the dummy gate structures.
10. The method of claim 9 , further comprising, after forming the first metal gate and the second metal gate, performing a chemical mechanical polishing process to expose a top surface of the interlayer dielectric layer.
11. The method of claim 10 , wherein the chemical mechanical polishing process removes the hard mask.
12. The method of claim 1 , wherein the first metal gate comprises a first work function metal layer, a first barrier layer, and a first metal gate material layer disposed sequentially from bottom to top, and the second metal gate comprises a second work function metal layer, a second barrier layer, and a second metal gate material layer disposed sequentially from bottom to top.
13. The method of claim 12 , wherein the first work function metal layer comprises one or more metals or metal compounds having a suitable metal material used for a NMOS device, and wherein the second work function metal layer comprises one or more metals or metal compounds having a suitable metal material used for a PMOS device.
14. The method of claim 12 , further comprising a capping layer between the first high-K dielectric layer and the first work function metal layer and between the second high-K dielectric layer and the second work function metal layer, wherein the capping layer comprises titanium nitride or tantalum nitride.
15. The method of claim 1 , further comprising forming an interface layer between the first high-K dielectric layer and the semiconductor substrate and between the second high-K dielectric layer and the semiconductor substrate, wherein the interface layer comprises silicon oxide.
16. The method of claim 1 , wherein the first and second high-K dielectric layers each have a dielectric constant greater than 3.9; wherein the sacrificial gate material layer comprises polysilicon, silicon nitride, or amorphous carbon; wherein the sacrificial dielectric layer comprises silicon dioxide; wherein the hard mask comprises SiN or BN.