On-chip probe circuit for detecting faults in an FPGA

1. An integrated programmable logic circuit comprising:

a plurality of programmable logic circuits having internal circuit nodes;

a plurality of flip flops, each flip flop having an asynchronous data input line, an asynchronous load line, and a data output connected to an internal circuit node;

a probe-data line;

an address circuit coupled to address lines for selecting one of the internal circuit nodes;

a read-probe enable line for selectively coupling the selected one of the internal circuit nodes to the probe-data line;

a data input path to the asynchronous data input line of each flip flop;

a write-probe data input path to the asynchronous data input line of each flip flop;

a write-probe enable line; and

selection circuitry, responsive to the address circuit and the write-probe enable line, selectively coupling one of the data input path and the write-probe data input path to the asynchronous data input of a selected flip flop.

2. The integrated circuit of claim 1 , further including a tri-state buffer coupled between the output of the selected internal circuit node and the data probe line, an enable input of the tri-state buffer coupled to the read-probe enable line.

3. The integrated circuit of claim 2 wherein the enable input of the tri-state buffer comprises a pair of complementary enable input; and

the read-probe enable line comprises a pair of complementary enable lines.

4. The integrated circuit of claim 1 wherein the address circuit comprises logic gates coupled between the internal circuit nodes, the address lines and the tri-state buffer.

5. The integrated circuit of claim 1 wherein the address lines, the write probe enable line and the read probe enable line are driven by a microcontroller through a row decoder.

6. The integrated circuit of claim 1 wherein the write-probe data input path is driven by a microcontroller through a column decoder.

7. In an integrated circuit including programmable logic circuitry including a plurality of flip flops arranged in a plurality of rows and columns, each flip flop having an asynchronous data input line, an asynchronous load line, and a data output, a read-write probe circuit for the flip flops comprising:

a probe data line;

a probe-data/column-select line;

a first address circuit coupled to first address lines for choosing a selected flip flop from a first group of the plurality of flip flops;

a first read-probe enable line for selectively coupling the data output of the selected flip flop from the first group to the probe-data line;

a second address circuit coupled to second address lines for choosing a selected flip flop from a second group of the plurality of flip flops;

a second read-probe enable line for selectively coupling the data output of the selected flip flop from the second group to the probe-data/column-select line;

a data input path to the asynchronous data input line of each flip flop;

a write-probe data input path from the probe data line to the asynchronous data input line of each flip flop;

a write-probe enable line;

first selection circuitry coupled to the probe-data/column-select line, the write-probe enable line and the first address circuit, to selectively couple one of the data input path and the write-probe data input path to the asynchronous data input of the selected flip flop from the first group; and

second selection circuitry coupled to the probe-data/column-select line, the write-probe enable line and the second address circuit, to selectively couple one of the data input path and the write-probe data input path to the asynchronous data input of the selected flip flop from the second group.

8. The integrated circuit of claim 7 , further including:

a first tri-state buffer coupled between the output of the selected flip flop from the first group and the data probe line, an enable input of the first tri-state buffer coupled to the first read-probe enable line; and

a second tri-state buffer coupled between the output of the selected flip flop from the second group and the data probe line, an enable input of the second tri-state buffer coupled to the second read-probe enable line.

9. The integrated circuit of claim 7 wherein:

the enable input of the first and second tri-state buffers comprises a pair of complementary enable inputs; and

the first and second read-probe enable lines each comprise a pair of complementary enable lines.

10. The integrated circuit of claim 7 wherein:

the first address circuit comprises logic gates coupled between the data outputs of the flip flops, the first address lines and the first tri-state buffer; and

the second address circuit comprises logic gates coupled between the data outputs of the flip flops, the second address lines and the second tri-state buffer.

11. The integrated circuit of claim 7 wherein the first and second address lines, the write probe enable line, and the read probe enable line are driven by a microcontroller through a row decoder.

12. The integrated circuit of claim 7 wherein the write-probe data input path and the probe-data/column-select line are driven by a microcontroller through a column decoder.

13. A method for probing a sequential logic device in a programmable logic device, comprising:

directly addressing a sequential logic device in the programmable logic device;

providing test input data directly to a data input of the sequential logic device;

enabling a write input to the sequential logic device; and

providing a write command to the sequential logic device to load the test input data into the sequential logic device.

14. The method of claim 13 , further including:

directly addressing an internal node of the programmable device; and

sensing a logic value on the internal node.

15. The method of claim 14 , wherein directly addressing an internal node of the programmable device comprises directly addressing an output of a sequential logic device.

16. The method of claim 15 wherein directly addressing an output of a sequential logic device comprises directly addressing the output of the sequential logic device to which test input data was provided.

17. The method of claim 15 wherein directly addressing a sequential logic device in the programmable logic device, providing test input data directly to a data input of the sequential logic device, enabling a write input to the sequential logic device, and providing a write command to the sequential logic device to load the test input data into the sequential logic device are performed by a microcontroller internal to the programmable logic device.

18. The method of claim 17 wherein directly addressing a plurality of flip flops in the programmable logic device, providing test input data having a selected logic level directly to a data input of each of the plurality of flip flops, enabling a write input to each of the plurality of flip flops, providing a write command to each of the plurality of flip flops to load the test input data into each of the plurality of flip flops, reading output data at outputs of each of the plurality of flip flops, and comparing the test input data and output data of each of the plurality of flip flops are performed by a microcontroller internal to the programmable logic device.

19. A method for probing flip-flops in a programmable logic device, comprising:

directly addressing a plurality of flip flops in the programmable logic device;

providing test input data directly to a data input of each of the plurality of flip flops;

enabling a write input to each of the plurality of flip flops;

providing a write command to each of the plurality of flip flops to load the test input data into each of the plurality of flip flops;

reading output data at outputs of each of the plurality of flip flops; and

comparing the test input data and output data of each of the plurality of flip flops.