Semiconductor integrated circuit device with reduced leakage current
The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A semiconductor integrated circuit device comprising:
a memory cell array including a plurality of memory cells arranged in a matrix having rows and columns;
word lines provided for the rows, respectively;
data line pairs provided for the columns, respectively;
a source lines connected to the plurality of memory cells, and
a potential control circuit configured to control a potential of the source line,
wherein each of the plurality of memory cells includes
a first P-channel MOS transistor having a gate electrode connected to a first storage node, a drain electrode connected to a second storage node and a source electrode to which an power supply voltage is applied,
a second P-channel MOS transistor having a gate electrode connected to the second storage node, a drain electrode connected to the first storage node and a source electrode to which an power supply voltage is applied,
a first N-channel MOS transistor having a gate electrode connected to the first storage node, a drain electrode connected to the second storage node and a source electrode connected to the source line,
a second N-channel MOS transistor having a gate electrode connected to the second storage node, a drain electrode connected to the first storage node and a source electrode connected to the source line;
a third N-channel MOS transistor making a current pass between the first storage node and one data line of one of the data line pairs and having a gate electrode connected to one of the word lines, and
a fourth N-channel MOS transistor making a current pass between the second storage node and another data line of the one data line pair and having a gate electrode connected to the one the word line,
wherein the potential control circuit controls the potential of the source line to a first potential value in a operation state and to a second potential value larger than the first potential value in a standby state, so that a gate tunnel leakage current between the gate electrode and the source electrode of the first P-channel MOS transistor and a gate tunnel leakage current between the gate electrode and source electrode of the second N-channel transistor can be reduced in the standby state compared to in the operation state.
2. The semiconductor integrated circuit device according to claim 1 , further comprising word drivers connected to the word lines, respectively, and providing the connected word lines with a potential of the first potential value when the potential of the source line has the second potential.
3. The semiconductor integrated circuit device according to claim 2 , wherein both of each data line pair are configured to have a potential value higher than the second potential value when the source line has the second potential value.
4. The semiconductor integrated circuit device according to claim 3 , wherein both of each data line pair are configured to have the potential value lower than the power supply voltage of the respective source electrodes of the first and second p-channel MOS transistors when the source line has the second potential value.
5. The semiconductor integrated circuit device according to claim 1 , wherein substrate electrodes of the first to fourth n-channel MOS transistors have a voltage of the first voltage value when the potential of the source line has the first potential value and the second potential value.
6. The semiconductor integrated circuit device according to claim 1 ,
wherein each of the first and second P-channel MOS transistors has a gate insulation film of a 4 nm or less thickness, and each of the first to fourth N-channel MOS transistors has a gate insulation film of a 4 nm or less thickness.