Three-dimensional semiconductor memory devices
Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
1. A nonvolatile memory device, comprising:
a substrate having a well region of second conductivity type therein;
a recess in the substrate, the recess extending into the well region;
a semiconductor plug in the recess, the semiconductor plug having an upper surface that is elevated relative to a surface of the substrate;
a vertical stack of nonvolatile memory cells on the substrate, the vertical stack of nonvolatile memory cells comprising:
a vertical stack of spaced-apart gate electrodes on the substrate;
a vertical active region on sidewalls of the vertical stack of spaced-apart gate electrodes and connected to the semiconductor plug; and
gate dielectric layers extending between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region; and
a first selection transistor extending between the vertical stack of nonvolatile memory cells and the substrate, the selection transistor having a gate electrode extending opposite a side of the semiconductor plug.
2. The memory device of claim 1 , wherein the gate dielectric layers of the vertical stack of nonvolatile memory cells comprise different materials relative to a gate dielectric layer of the first selection transistor.
3. The memory device claim 2 , wherein each of the gate dielectric layers comprises a composite of a tunnel insulating layer, a charge storage layer on the tunnel insulating layer, a barrier dielectric layer on the charge storage layer and a blocking insulating layer on the barrier dielectric layer, and wherein the barrier dielectric layer comprises a material having a greater bandgap relative to the blocking insulating layer.
4. The memory device claim 1 , wherein the substrate comprises a common source region of first conductivity type on the well region, and wherein the recess extends through the common source region and into the well region.
5. The memory device claim 1 , further comprising a second selection transistor extending between the vertical stack of nonvolatile memory cells and the first selection transistor, the second selection transistor having a gate electrode extending opposite the side of the semiconductor plug.
6. A nonvolatile memory device, comprising:
a lower structure including a lower gate pattern on a substrate and a lower active pattern penetrating the lower gate pattern, the lower active pattern being electrically connected to the substrate; and
an upper structure including upper gate patterns stacked on the lower structure, an upper active pattern penetrating the upper gate patterns, and a vertical insulator disposed between the upper active pattern and the upper gate patterns, the upper active pattern being electrically connected to the lower active pattern,
wherein the lower active pattern has a non-planar upper surface.
7. The memory device claim 6 , wherein the vertical insulator is in contact with a portion of the upper surface of the lower active pattern.
8. The memory device claim 6 , wherein the vertical insulator includes a bottom portion covering a portion of the upper surface of the lower active pattern and a sidewall portion extended from the bottom portion and covering a sidewall of the upper active pattern.
9. The memory device claim 6 , wherein the substrate comprises a well region of second conductivity type and a common source region of first conductivity type on the well region, and wherein the lower active pattern is in contact with the well region and the common source region.
10. The memory device claim 9 , wherein a bottom surface of the lower active pattern is in contact with the well region, and a portion of a sidewall of the lower active pattern is in contact with the common source region.
11. A nonvolatile memory device, comprising:
a substrate having a well region of second conductivity type therein and a common source region of first conductivity type on the well region;
a stack-structure on the substrate, the stack-structure including insulation patterns and gate patterns that are stacked alternately and repeatedly; and
a vertical active pattern penetrating the stack-structure and including a lower active pattern and an upper active pattern that are sequentially stacked,
wherein the lower active pattern fills a recess region formed in the substrate and contacts the well region.
12. The memory device claim 11 , wherein the lower active pattern passes through the common source region and has a bottom surface that is lower than a bottom surface of the common source region.
13. The memory device claim 11 , wherein the lower active pattern has a non-planar upper surface that is higher than an upper surface of the substrate.
14. The memory device claim 11 , wherein the lower active pattern is doped with a dopant having the same type as that of the well region.
15. The memory device claim 11 , further comprising a vertical insulator being vertically extended and disposed between the upper active pattern and the stack-structure.