Semiconductor device and passive component integration in a semiconductor package
According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.
1. A semiconductor package comprising:
a substrate having lower and upper surfaces;
at least one passive component coupled to first and second conductive pads and situated on said upper surface of said substrate;
at least one semiconductor device being directly coupled to said lower surface of said substrate through a third conductive pad, and electrically coupled to said at least one passive component;
said at least one semiconductor device having a first electrode for electrical and mechanical connection to a conductive pad external to and not disposed on said semiconductor package.
2. The semiconductor package of claim 1 , wherein said at least one semiconductor device has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.
3. The semiconductor package of claim 2 , wherein said at least one semiconductor device has a third electrode adjacent to said first electrode for electrical and mechanical connection to a conductive pad external to said semiconductor package.
4. The semiconductor package of claim 2 , wherein said first and second electrodes of said at least one semiconductor device are situated on opposing surfaces of said at least one semiconductor device.
5. The semiconductor package of claim 2 , wherein said at least one semiconductor device is a FET, wherein said first electrode is a source electrode of said FET and said second electrode is a drain electrode of said FET.
6. The semiconductor package of claim 1 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate and having a plurality of input/output electrodes.
7. The semiconductor package of claim 6 , wherein each of said input/output electrodes is electrically and mechanically coupled to one of a plurality of conductive pads on said upper surface of said substrate.
8. The semiconductor package of claim 6 further comprising a second conductive pad on said lower surface of said substrate, wherein said second conductive pad on said lower surface of said substrate is coupled to one of said plurality of input/output electrodes of said IC die.
9. The semiconductor package of claim 1 , wherein said at least one passive component is electrically and mechanically coupled to each of said first and second conductive pads by a conductive adhesive.
10. The semiconductor package of claim 1 , wherein said at least one semiconductor device is a GaN device.
11. A semiconductor package comprising:
a substrate having lower and upper surfaces;
at least one passive component situated on said upper surface of said substrate;
at least one power transistor being directly connect to said lower surface of said substrate through a first conductive pad;
said at least one passive component being electrically connected to said power transistor in said semiconductor package so as to form at least a portion of a power processing circuit.
12. The semiconductor package of claim 11 , wherein said at least one power transistor has a first electrode for electrical and mechanical connection to a second conductive pad external to and not disposed on said semiconductor package.
13. The semiconductor package of claim 11 , wherein said at least one power transistor has a second electrode electrically and mechanically coupled to said first conductive pad on said lower surface of said substrate.
14. The semiconductor package of claim 11 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate.
15. The semiconductor package of claim 11 further comprising an integrated circuit (IC) die situated on said upper surface of said substrate and electrically connected to said power transistor.
16. The semiconductor package of claim 15 , wherein said IC die comprises a controller for controlling said power transistor.
17. The semiconductor package of claim 11 , wherein said power processing circuit is a DC-DC converter.
18. The semiconductor package of claim 11 , wherein said at least one passive component comprises a bypass capacitor.
19. The semiconductor package of claim 11 , wherein said at least one passive component comprises an output capacitor.
20. The semiconductor package of claim 11 , wherein said at least one power transistor is a GaN device.