Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
1. A semiconductor die assembly, comprising:
a first semiconductor die;
a second semiconductor die carrying the first semiconductor die, the second semiconductor die having a peripheral portion extending laterally outward beyond at least one side of the first semiconductor die, wherein the first semiconductor die defines a first thermal path away from the second semiconductor die;
a thermal transfer feature at the peripheral portion of the second semiconductor die, wherein the thermal transfer feature is configured to define a second thermal path that transfers heat away from the second semiconductor die, the first thermal path being separate from the first semiconductor die, wherein the first and second thermal paths are laterally spaced apart and substantially perpendicular to one another, and wherein the second thermal path is generally parallel with the plane of the second die;
a plurality of thermally conductive elements disposed between the first and second semiconductor dies and extending from the first to the second semiconductor die, and wherein the thermally conductive elements are electrically isolated from the first and second semiconductor dies;
and a thermally conductive casing that is peripheral to the thermal transfer feature, wherein the thermally conductive casing is in thermal communication with the thermal transfer feature.
2. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die is one of a plurality of memory dies arranged in a stack;
the second semiconductor die is a logic die;
the memory dies are electrically coupled to one another and to the logic die by a plurality of through-silicon vias (TSVs) extending through the memory dies and a plurality of electrically conductive features between the memory dies and the logic die;
the thermal transfer feature is a first thermal transfer feature spaced laterally apart from the side of the first semiconductor dies and extending vertically from the peripheral portion of the logic die to at least an elevation corresponding to that of the memory die spaced furthest from the logic die;
the semiconductor die assembly further comprises—
a second thermal transfer feature on the stack;
and
a package substrate having a first side and a second side opposite the first side, wherein the logic die is electrically coupled to the package substrate at the first side and the package substrate includes electrical connectors at the second side.
3. The semiconductor die assembly of claim 1 wherein the first semiconductor die is one of a plurality of first semiconductor dies, and wherein the thermal transfer feature extends from the peripheral portion to an elevation corresponding to that of the first semiconductor die spaced furthest from the second semiconductor die.
4. The semiconductor die assembly of claim 1 wherein the thermal transfer feature comprises at least one of blank silicon, a thermal interface material, and silicon doped with thermally conductive fillers and wherein the thermally conductive elements are pillars, columns or studs.
5. The semiconductor die assembly of claim 1 wherein:
the thermal transfer feature is a first thermal transfer feature spaced laterally apart from the side of the first semiconductor die; and
the semiconductor die assembly further comprises a second thermal transfer feature superimposed with the first semiconductor die.
6. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die is one of a plurality of memory dies arranged in a stack;
the second semiconductor die is a logic die; and
the second thermal path is spaced laterally apart from the memory dies.
7. The semiconductor die assembly of claim 1 wherein thermally conductive casing extends at least partially around the first and second semiconductor dies.
8. The semiconductor die assembly of claim 7 wherein the thermally conductive casing is in thermal contact with the thermal transfer feature proximate the peripheral portion.
9. The semiconductor die assembly of claim 7 wherein the first semiconductor die is one of a plurality of first semiconductor dies arranged in a stack on the second semiconductor die, and wherein the thermally conductive casing is in thermal contact with the thermal transfer feature proximate the first semiconductor die spaced furthest from the second semiconductor die.
10. The semiconductor die assembly of claim 7 wherein the thermally conductive casing includes a stepped cavity configured to receive the peripheral portion.
11. The semiconductor die assembly of claim 7 wherein the thermally conductive casing includes a cavity configured to receive the first and second semiconductor dies and at least one thermally conductive member in the cavity.
12. The semiconductor die assembly of claim 7 wherein the thermally conductive casing includes a cavity configured to receive the first and second semiconductor dies and a flange extending laterally into the cavity, wherein the flange is thermally coupled to the thermal transfer feature at the peripheral portion.
13. The semiconductor die assembly of claim 1 wherein the thermally conductive casing has a cavity configured to receive the first semiconductor die and a base portion in thermal contact with the thermal transfer feature, and wherein the base portion is carried at least in part by the peripheral portion;
the assembly further comprising a package substrate carrying the second semiconductor die, wherein the thermally conductive casing terminates a distance from the package substrate.
14. A semiconductor die assembly, comprising:
a memory die having a first footprint;
a logic die carrying the memory die, the logic die having a second footprint larger than the first footprint such that the logic die includes a peripheral portion extending beyond the first footprint;
a thermal transfer feature aligned with the peripheral portion of the logic die, wherein the memory die defines a first thermal path and the thermal transfer feature defines a second thermal path thermally isolated from the first thermal path at the logic die, wherein the first and second thermal paths are spaced apart from each other laterally and at least substantially perpendicular to one another, and wherein the second thermal path is generally parallel with the plane of the logic die;
a plurality of thermally conductive elements disposed between the memory die and the logic die and extending from the memory die to the logic die, wherein the thermally conductive elements are made from copper, nickel, conductor-filled epoxy or combination thereof, and wherein the thermally conductive elements are electrically isolated from the memory die and the logic die; and
thermally conductive casing that is peripheral to the thermal transfer feature, wherein the thermally conductive casing is in thermal communication with the thermal transfer feature.
15. The semiconductor die assembly of claim 14 wherein the memory die is one of a plurality of memory dies electrically coupled together in a stack.
16. The semiconductor die assembly of claim 14 wherein the thermally conductive casing includes a cavity that is shaped generally similar to an outer boundary of the memory die and the logic die.
17. A semiconductor die assembly, comprising:
a memory die having a first footprint;
a logic die carrying the memory die, the logic die having a second footprint larger than the first footprint such that the logic die includes a peripheral portion extending beyond the first footprint;
a thermal transfer feature aligned with the peripheral portion of the logic die, wherein the memory die defines a first thermal path and the thermal transfer feature defines a second thermal path thermally isolated from the first thermal path at the logic die, wherein the first and second thermal paths are spaced apart from each other laterally and at least substantially perpendicular to one another, and wherein the second thermal path is generally parallel with the plane of the logic die, and wherein the logic die is between the second thermal path and a substrate of the semiconductor die assembly; and
a thermally conductive casing that is peripheral to the thermal transfer feature, wherein the thermally conductive casing is in thermal communication with the thermal transfer feature.
18. The semiconductor die assembly of claim 17 , further comprising a plurality of thermally conductive elements disposed between the first and second semiconductor dies and extending from the first to the second semiconductor die, wherein the thermally conductive elements are electrically isolated from the first and second semiconductor dies.
19. The semiconductor die assembly of claim 18 , wherein the thermally conductive elements are pillars, columns or studs.
20. The semiconductor die assembly of claim 18 , wherein the thermally conductive elements are made from copper, nickel, conductor-filled epoxy or combination thereof.
21. A semiconductor system, comprising:
a stacked semiconductor die assembly including—
a package substrate having a first side and a second side opposite the first side;
a logic die at the first side and electrically coupled to the package substrate;
a plurality of memory dies carried by the logic die and electrically coupled to one another and to the logic die, wherein the memory dies define a first thermal path that transfers heat away from the logic die, and wherein the logic die includes a peripheral portion extending laterally outward beyond at least one side of the memory dies;
a thermal transfer feature at the peripheral portion, wherein the thermal transfer feature defines a second thermal path that transfers heat away from the logic die, the second thermal path being separate from the memory dies, wherein the first and second thermal paths are spaced apart from each other laterally and at least substantially perpendicular to one another, and wherein the second thermal path is generally parallel with the plane of the logic die;
a plurality of thermally conductive elements disposed between the memory die and the logic die and extending from the memory die to the logic die, and wherein the thermally conductive elements are electrically isolated from the memory die and the logic die; and
a thermally conductive casing that is peripheral to the thermal transfer feature, wherein the thermally conductive casing is in the thermal communication with the thermal transfer feature; and
a driver electrically coupled to the second side of the package substrate.