IP Library Granted Patent US 9,178,012
Granted Patent B2
US 9,178,012 · App. 14/174,887 · Granted Nov 3, 2015

Plated trench capacitor structures

Inventors: Veeraraghavan S. Basker (Schenectady, NY); Richard Q. Williams (Essex Junction, VT)
Assignee: GLOBALFOUNDRIES U.S. 2 LLC
H01L28/60H01L27/108H01L28/91H01L29/66181H01L27/10861H01L29/945
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,178,012
App. No.
14/174,887
Granted
Nov 3, 2015
Kind
B2
Abstract

A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.

Claims (20)

1. A structure, comprising:

a semiconductor substrate;

a trench in the semiconductor substrate and in alignment with an opening in a plurality of upper layers covering the semiconductor substrate;

a conformal metal plate lining exposed surfaces of the trench;

a dielectric liner on the conformal metal plate;

a metal inner electrode on the dielectric liner;

a contact in contact with the metal inner electrode; and

an oxide cap within the opening and on any exposed top surfaces of the conformal metal plate, the dielectric liner, and the metal inner electrode,

wherein the contact extends through the oxide cap and into contact with at least a portion of the metal inner electrode.

2. The structure of claim 1 , wherein the semiconductor substrate is a single uniformly doped layer of silicon substrate.

3. The structure of claim 1 , wherein the upper layers comprise:

an insulator layer on the semiconductor substrate;

a semiconductor layer on the insulator layer; and

a pad layer on the semiconductor layer.

4. The structure of claim 1 , wherein the conformal metal plate is lining all exposed surfaces of the trench.

5. The structure of claim 1 , wherein the conformal metal plate is comprised of platinum or gold.

6. The structure of claim 5 , wherein the dielectric liner is comprised of a high-k material.

7. The structure of claim 6 , wherein the metal inner electrode is comprised of a polysilicon film.

8. The structure of claim 7 , wherein the contact is in contact with an upper surface of the metal inner electrode.

9. The structure of claim 1 , further comprising a hardmask material lining exposed surfaces of the upper layers in the opening to isolate the exposed surfaces of the upper layers.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2014
From: BASKER, VEERARAGHAVAN S.; WILLIAMS, RICHARD Q.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 032169/0289 →
Continuity (2)
Division 13269955 · Oct 10, 2011
Related Publication 20140151850A1 · Jun 5, 2014