System and method for performing address-based SRAM access assists

1. A method comprising:

generating an access assist map that specifies at least one storage cell of a memory array for which access assist is enabled, where generating the access assist map comprises:

accessing the memory array with the access assist disabled;

identifying failing storage cells of the memory array;

accessing the failing storage cells of the memory array with the access assist enabled; and

indicating, in the access assist map, the failing storage cells that pass with the access assist enabled;

receiving an address for a memory access;

determining, based on the address, that the access assist is enabled for the at least one storage cell of the memory array corresponding to the address; and

applying the access assist to the at least one storage cell to perform the memory access.

2. The method of claim 1 , wherein the access assist comprises at least one of bitline voltage boosting, wordline voltage boosting, and supply voltage boosting.

3. The method of claim 2 , wherein the access assist specifies a level of voltage boosting.

4. The method of claim 1 , where applying the access assist comprises:

applying a first access assist variation to a first storage cell of the at least one storage cell; and

simultaneously applying a second access assist variation to a second storage cell of the at least one storage cell.

5. The method of claim 1 , further comprising receiving a non-address condition and determining that the access assist is enabled is based on the non-address condition.

6. The method of claim 5 , wherein the non-address condition comprises one or more of a measured temperature, a measured supply voltage, an operating frequency, aging factor, and a scaled supply voltage.

7. The method of claim 5 , wherein the non-address condition comprises one or more of a read operation or a write operation.

8. The method of claim 5 , further comprising modifying the access assist based on the non-address condition.

9. The method of claim 1 , wherein the access assist map specifies a variation of the access assist to be applied to the at least one storage cell.

10. The method of claim 1 , wherein the access assist map specifies a first variation of the access assist for a first storage cell corresponding to the address and specifies a second variation of the access assist for a second storage cell corresponding to the address.

11. The method of claim 1 , further comprising allocating a portion of the memory array based on the access assist map.

12. The method of claim 1 , wherein the

access assist map specifies a first storage cell for which the access assist is enabled for a first operating condition and, further comprising

generating a second access assist map that specifies a second storage cell for which the access assist is enabled for a second operating condition.

13. A method comprising:

generating a first access assist map that specifies a first storage cell of a memory array for which a first variation of access assist is enabled for an operating condition;

generating a second assist map that specifies the first storage cell for which a second variation of the access assist is enabled for the operating condition;

receiving an address for a memory access, wherein the address corresponds to the first storage cell;

determining, based on the address, that the access assist is enabled for the first storage cell; and

applying the access assist to the first storage cell to perform the memory access.

14. The method of claim 1 , further comprising replacing a faulty storage cell with a redundant storage cell.

15. An integrated circuit comprising:

a memory array of storage cells; and

an access assist circuit that is coupled to the memory array of storage cells and configured to:

generate an access assist map that specifies at least one storage cell of the memory array for which access assist is enabled, where generating the access assist map comprises:

accessing the memory cell array with the access assist disabled;

identifying failing storage cells of the memory array;

accessing the failing storage cells of the memory array with the access assist enabled; and

indicating, in the access assist map, the failing storage cells that pass with the access assist enabled;

receive an address for a memory access;

determine, based on the address, that access assist is enabled for at least one storage cell of the memory array corresponding to the address; and

apply the access assist to the at least one storage cell to perform the memory access.

16. The integrated circuit of claim 15 , wherein the access assist comprises at least one of bitline voltage boosting, wordline voltage boosting, and supply voltage boosting.

17. The integrated circuit of claim 16 , wherein the access assist specifies a level of voltage boosting.

18. The integrated circuit of claim 15 , wherein the access assist circuit is further configured to receive a non-address condition and determine that the access assist is enabled is based on the non-address condition.

19. The integrated circuit of claim 15 , wherein the access assist map specifies a variation of the access assist to be applied to the at least one storage cell.

20. The integrated circuit of claim 15 , wherein the access assist map specifies a first variation of the access assist for a first storage cell corresponding to the address and specifies a second variation of the access assist for a second storage cell corresponding to the address.